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Analog-to-Digital Converters: Digitizing the Analog World

Type: Journal Paper

Author : Hae-Seung Lee; Sodini, C.G.

Year: 2008

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A high-speed CMOS comparator for use in an ADC

Type: Journal Paper

Author : McCarroll, B.J.; Sodini, C.G.; Lee, H.-S.

Year: 1988

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A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging

Type: Conference Paper

Author : Kailiang Chen , Hae-Seung Lee , Sodini, C.G.

Publisher: IEEE

Year: 2014

Wireless behind-the-ear EEG recording device with wireless interface to a mobile device (iPhone/iPod touch)

Type: Conference Paper

Author : Do Valle, B.G.; Cash, S.S.; Sodini, C.G.

Publisher: IEEE

Year: 2014

A 256×256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output

Type: Journal Paper

Author : Decker, S.; McGrath, D.; Brehmer, K.; Sodini, C.G.

Year: 1998

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Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

Type: Journal Paper

Author : Fiorenza, J.K.; Sepke, T.; Holloway, P.; Sodini, C.G.; Hae-Seung Lee

Publisher: IEEE

Year: 2006

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[IEEE 2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San Francisco, CA (2006.02.6-2006.02.9)] 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers - Comparator-based switched-capacitor circuits for scaled CMOS technologies

Type: Journal Paper

Author : Sepke, T.; Fiorenza, J.K.; Sodini, C.G.; Holloway, P.; Hae-Seung Lee,

Year: 2006

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Bias-Stress Effect in Pentacene Organic Thin-Film Transistors

Type: Journal Paper

Author : Ryu, K.K.; Nausieda, I.; He, D.D.; Akinwande, A.I.; Bulovic, V.; Sodini, C.G.

Publisher: IEEE

Year: 2010

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A column-row-parallel ultrasound imaging architecture for 3d plane-wave imaging and Tx 2nd-order harmonic distortion (HD2) reduction

Type: Conference Paper

Author : Kailiang Chen; Byung Chul Lee; Thomenius, K.; Khuri-Yakub, B.T.; Hae-Seung Lee; Sodini, C.G.

Publisher: IEEE

Year: 2014

Si/Si1-xGex valence band discontinuity measurements using a semiconductor-insulator-semiconductor (SIS) heterostructure

Type: Journal Paper

Author : Gan, C.H.; del Alamo, J.A.; Bennett, B.R.; Meyerson, B.S.; Crabbe, E.F.; Sodini, C.G.; Reif, L.R.

Publisher: IEEE

Year: 1994

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Analog-to-Digital Converters: Digitizing the Analog World

A high-speed CMOS comparator for use in an ADC

A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging

Wireless behind-the-ear EEG recording device with wireless interface to a mobile device (iPhone/iPod touch)

A 256×256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

[IEEE 2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San Francisco, CA (2006.02.6-2006.02.9)] 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers - Comparator-based switched-capacitor circuits for scaled CMOS technologies

Bias-Stress Effect in Pentacene Organic Thin-Film Transistors

A column-row-parallel ultrasound imaging architecture for 3d plane-wave imaging and Tx 2nd-order harmonic distortion (HD2) reduction

Si/Si1-xGex valence band discontinuity measurements using a semiconductor-insulator-semiconductor (SIS) heterostructure

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Analog-to-Digital Converters: Digitizing the Analog World

A high-speed CMOS comparator for use in an ADC

A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging

Wireless behind-the-ear EEG recording device with wireless interface to a mobile device (iPhone/iPod touch)

A 256×256 CMOS imaging array with wide dynamic range pixels and column-parallel digital output

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies

[IEEE 2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers - San Francisco, CA (2006.02.6-2006.02.9)] 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers - Comparator-based switched-capacitor circuits for scaled CMOS technologies

Bias-Stress Effect in Pentacene Organic Thin-Film Transistors

A column-row-parallel ultrasound imaging architecture for 3d plane-wave imaging and Tx 2nd-order harmonic distortion (HD2) reduction

Si/Si1-xGex valence band discontinuity measurements using a semiconductor-insulator-semiconductor (SIS) heterostructure