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Corrections to “Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference” [Jun 12 331-335]

Type: Journal Paper

Author : Pu, Xumin; Kumar, Ajit; Nagaraj, Kanthi

Publisher: IEEE

Year: 2014

Analysis of phase variation of CMOS digital attenuator

Type: Journal Paper

Author : Pinping Sun

Publisher: IET

Year: 2014

Hypergraph clustering-based Cloud Manufacturing Service Management method

Type: Conference Paper

Author : Lei Wu , Minggang He , Yanyan Han

Publisher: IEEE

Year: 2014

CMOS Compatible Fabrication Processes for the Digital Micromirror Device

Type: Journal Paper

Author : Cuiling Gong; Hogan, Tim

Publisher: IEEE

Year: 2014

Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS

Type: Journal Paper

Author : Mohamed, Mohamed /I/. /A/.; Mohammed, Kadri; Daneshrad, B.

Publisher: IEEE

Year: 2014

MASTER: A Multicore Cache Energy-Saving Technique Using Dynamic Cache Reconfiguration

Type: Journal Paper

Author : Mittal, Sparsh; Yanan Cao; Zhao Zhang

Publisher: IEEE

Year: 2014

Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture

Type: Journal Paper

Author : Jen-Wei Lee; Szu-Chi Chung; Hsie-Chia Chang; Chen-Yi Lee

Publisher: IEEE

Year: 2014

High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology

Type: Journal Paper

Author : Ching-Che Chung; Duo Sheng; Sung-En Shen

Publisher: IEEE

Year: 2014

A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold

Type: Journal Paper

Author : Keller, S.; Harris, David Money; Martin, Alain J.

Publisher: IEEE

Year: 2014

A 60-dB Gain OTA Operating at 0.25-V Power Supply in 130-nm Digital CMOS Process

Type: Journal Paper

Author : Ferreira, Luis H. C.; Sonkusale, Sameer R.

Publisher: IEEE

Year: 2014

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Corrections to “Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference” [Jun 12 331-335]

Analysis of phase variation of CMOS digital attenuator

Hypergraph clustering-based Cloud Manufacturing Service Management method

CMOS Compatible Fabrication Processes for the Digital Micromirror Device

Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS

MASTER: A Multicore Cache Energy-Saving Technique Using Dynamic Cache Reconfiguration

Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture

High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology

A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold

A 60-dB Gain OTA Operating at 0.25-V Power Supply in 130-nm Digital CMOS Process

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Corrections to &#x201C;Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference&#x201D; [Jun 12 331-335]

Analysis of phase variation of CMOS digital attenuator

Hypergraph clustering-based Cloud Manufacturing Service Management method

CMOS Compatible Fabrication Processes for the Digital Micromirror Device

Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS

MASTER: A Multicore Cache Energy-Saving Technique Using Dynamic Cache Reconfiguration

Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture

High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology

A Compact Transregional Model for Digital CMOS Circuits Operating Near Threshold

A 60-dB Gain OTA Operating at 0.25-V Power Supply in 130-nm Digital CMOS Process

Corrections to “Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference” [Jun 12 331-335]