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A layered approach for testing timing in the model-based implementation

date accessioned2020-03-12T19:40:33Z
date available2020-03-12T19:40:33Z
date issued2014
identifier other6800403.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/985801?locale-attribute=fa&show=full
formatgeneral
languageEnglish
publisherIEEE
titleA layered approach for testing timing in the model-based implementation
typeConference Paper
contenttypeMetadata Only
identifier padid8101499
subject keywordsCMOS integrated circuits
subject keywordsadaptive equalisers
subject keywordsanalogue-digital conversion
subject keywordsblind equalisers
subject keywordsclock and data recovery circuits
subject keywordsdecision feedback equalisers
subject keywordsinterpolation
subject keywordsradio receivers
subject keywordsCDR
subject keywordsCMOS
subject keywordsDFE
subject keywordsadaptive CTLE
subject keywordsanalog phase interpolator
subject keywordsblind ADC
subject keywordsclock and data recovery circuits
subject keywordscontinuous time linear equalizer
subject keywordsdecision feedback equalizers
subject keywordsdigital data interpolation
subject keywordsphase tracking ADC
subject keywordsBackplanes
subject keywordsCMOS integrated circuits
subject keywordsDecision feedback equalizers
subject keywordsInterpolation
subject keywordsLeast square
identifier doi10.1109/CICC.2014.6946102
journal titleesign, Automation and Test in Europe Conference and Exhibition (DATE), 2014
filesize838981
citations0
contributor rawauthorBaekGyu Kim , Hwang, H.I. , Taejoon Park , Son, S.H. , Insup Lee


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