Design and FPGA Implementation of High-Speed, Fixed-Latency Serial Transceivers
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: 2014DOI: 10.1109/TNS.2013.2296301
Keyword(s): clocks,field programmable gate arrays,transceivers,tuning,SerDes transceivers,Xilinx Virtex 5 FPGA,changeable delay tuning,dynamic clock phase shifting,field programmable gate arrays,fixed-latency serial links,fixed-latency serial transceivers,reset-relock process,roulette approach,serializer-deserializer chips,Clocks,Delays,Field programmable gate arrays,Phase locked loops,Receivers,Transceivers,Tuning,Changeable delay tuning,FPGA,SerDes transceiver,dynamic clock phase s
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Design and FPGA Implementation of High-Speed, Fixed-Latency Serial Transceivers
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| contributor author | Xue Liu | |
| contributor author | Qing-Xu Deng | |
| contributor author | Ze-Ke Wang | |
| date accessioned | 2020-03-12T18:43:31Z | |
| date available | 2020-03-12T18:43:31Z | |
| date issued | 2014 | |
| identifier issn | 0018-9499 | |
| identifier other | 6728654.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/968217?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Design and FPGA Implementation of High-Speed, Fixed-Latency Serial Transceivers | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8002305 | |
| subject keywords | clocks | |
| subject keywords | field programmable gate arrays | |
| subject keywords | transceivers | |
| subject keywords | tuning | |
| subject keywords | SerDes transceivers | |
| subject keywords | Xilinx Virtex 5 FPGA | |
| subject keywords | changeable delay tuning | |
| subject keywords | dynamic clock phase shifting | |
| subject keywords | field programmable gate arrays | |
| subject keywords | fixed-latency serial links | |
| subject keywords | fixed-latency serial transceivers | |
| subject keywords | reset-relock process | |
| subject keywords | roulette approach | |
| subject keywords | serializer-deserializer chips | |
| subject keywords | Clocks | |
| subject keywords | Delays | |
| subject keywords | Field programmable gate arrays | |
| subject keywords | Phase locked loops | |
| subject keywords | Receivers | |
| subject keywords | Transceivers | |
| subject keywords | Tuning | |
| subject keywords | Changeable delay tuning | |
| subject keywords | FPGA | |
| subject keywords | SerDes transceiver | |
| subject keywords | dynamic clock phase s | |
| identifier doi | 10.1109/TNS.2013.2296301 | |
| journal title | Nuclear Science, IEEE Transactions on | |
| journal volume | 61 | |
| journal issue | 1 | |
| filesize | 1594981 | |
| citations | 0 |