Erratum to “Test Time Reduction in EDT Bandwidth Management for SoC Designs” [Nov 13 1776-1786]
| contributor author | Janicki, Jakub | |
| contributor author | Kassab, M. | |
| contributor author | Mrugalski, Grzegorz | |
| contributor author | Mukherjee, Nandini | |
| contributor author | Rajski, J. | |
| contributor author | Tyszer, J. | |
| date accessioned | 2020-03-12T18:36:35Z | |
| date available | 2020-03-12T18:36:35Z | |
| date issued | 2014 | |
| identifier issn | 0278-0070 | |
| identifier other | 6685876.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/964227?locale-attribute=fa&show=full | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Erratum to “Test Time Reduction in EDT Bandwidth Management for SoC Designs” [Nov 13 1776-1786] | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 7997691 | |
| subject keywords | Automatic test equipment | |
| subject keywords | Bandwidth | |
| subject keywords | Integrated circuit testing | |
| subject keywords | Optimization | |
| subject keywords | System-on-chip | |
| identifier doi | 10.1109/TCAD.2013.2292631 | |
| journal title | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on | |
| journal volume | 33 | |
| journal issue | 1 | |
| filesize | 544594 | |
| citations | 0 |
Files in this item
| Files | Size | Format | View |
|---|---|---|---|
|
There are no files associated with this item. |
|||