Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit
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: 2014DOI: 10.1109/TVLSI.2013.2269616
Keyword(s): CMOS integrated circuits,clock and data recovery circuits,linearisation techniques,phase detectors,synchronisation,timing circuits,CMOS technology,binary phase detectors,collaborative timing recovery circuit,finite latency difference,linear information,linear loop dynamics,linearization technique,multichannel clock and data recovery circuit,phase errors,size 45 nm,Binary phase detector (PD),clock and data recovery circuit (CDR),digital control,linearization techniques,serial
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Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit
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| contributor author | Byoung-Joo Yoo | |
| contributor author | Woo-Rham Bae | |
| contributor author | Jiho Han | |
| contributor author | Jaeha Kim | |
| contributor author | Deog-Kyoon Jeong | |
| date accessioned | 2020-03-12T18:24:38Z | |
| date available | 2020-03-12T18:24:38Z | |
| date issued | 2014 | |
| identifier issn | 1063-8210 | |
| identifier other | 6549110.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/957554?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 7989839 | |
| subject keywords | CMOS integrated circuits | |
| subject keywords | clock and data recovery circuits | |
| subject keywords | linearisation techniques | |
| subject keywords | phase detectors | |
| subject keywords | synchronisation | |
| subject keywords | timing circuits | |
| subject keywords | CMOS technology | |
| subject keywords | binary phase detectors | |
| subject keywords | collaborative timing recovery circuit | |
| subject keywords | finite latency difference | |
| subject keywords | linear information | |
| subject keywords | linear loop dynamics | |
| subject keywords | linearization technique | |
| subject keywords | multichannel clock and data recovery circuit | |
| subject keywords | phase errors | |
| subject keywords | size 45 nm | |
| subject keywords | Binary phase detector (PD) | |
| subject keywords | clock and data recovery circuit (CDR) | |
| subject keywords | digital control | |
| subject keywords | linearization techniques | |
| subject keywords | serial | |
| identifier doi | 10.1109/TVLSI.2013.2269616 | |
| journal title | Very Large Scale Integration (VLSI) Systems, IEEE Transactions on | |
| journal volume | 22 | |
| journal issue | 6 | |
| filesize | 1624727 | |
| citations | 0 |