Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs
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: 2014DOI: 10.1109/TVLSI.2013.2252031
Keyword(s): MOSFET,SRAM chips,logic design,technology CAD (electronics),asymmetric gate workfunction FinFET SRAM,fin pitches,mixed mode 2D TCAD technology circuit codesign methodology,mixed mode transient device simulations,multigate FET technology,parasitic capacitances,parasitics aware design,planar CMOS technology,silicon on insulator process,size 22 nm,structure synthesis algorithms,transport analysis,FinFET,SRAM,multigate FET,parasitics,structure synthesis
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Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs
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| contributor author | Bhoj, Ajay N. | |
| contributor author | Jha, Niraj K. | |
| date accessioned | 2020-03-12T18:22:47Z | |
| date available | 2020-03-12T18:22:47Z | |
| date issued | 2014 | |
| identifier issn | 1063-8210 | |
| identifier other | 6502262.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/956499?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs | |
| type | Journal Paper | |
| contenttype | Metadata Only | |
| identifier padid | 7988542 | |
| subject keywords | MOSFET | |
| subject keywords | SRAM chips | |
| subject keywords | logic design | |
| subject keywords | technology CAD (electronics) | |
| subject keywords | asymmetric gate workfunction FinFET SRAM | |
| subject keywords | fin pitches | |
| subject keywords | mixed mode 2D TCAD technology circuit codesign methodology | |
| subject keywords | mixed mode transient device simulations | |
| subject keywords | multigate FET technology | |
| subject keywords | parasitic capacitances | |
| subject keywords | parasitics aware design | |
| subject keywords | planar CMOS technology | |
| subject keywords | silicon on insulator process | |
| subject keywords | size 22 nm | |
| subject keywords | structure synthesis algorithms | |
| subject keywords | transport analysis | |
| subject keywords | FinFET | |
| subject keywords | SRAM | |
| subject keywords | multigate FET | |
| subject keywords | parasitics | |
| subject keywords | structure synthesis | |
| identifier doi | 10.1109/TVLSI.2013.2252031 | |
| journal title | Very Large Scale Integration (VLSI) Systems, IEEE Transactions on | |
| journal volume | 22 | |
| journal issue | 3 | |
| filesize | 2365974 | |
| citations | 0 |