Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
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: 2009DOI: 10.1109/HPCA.2009.4798252
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Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
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| contributor author | Reetuparna Das | |
| contributor author | Soumya Eachempati | |
| contributor author | Asit K. Mishra | |
| contributor author | Vijaykrishnan Narayanan | |
| contributor author | Chita R. Das | |
| date accessioned | 2020-03-14T11:28:11Z | |
| date available | 2020-03-14T11:28:11Z | |
| date issued | 2009 | |
| identifier other | J7BjsFU4Gnrm3q8WPiErVg01JXp99cPuKYl0YLP8kQEnHBAEqF.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/1632033?locale-attribute=en | |
| format | general | |
| language | English | |
| title | Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs | |
| type | Journal Paper | |
| contenttype | Fulltext | |
| contenttype | Fulltext | |
| identifier padid | 11764437 | |
| identifier doi | 10.1109/HPCA.2009.4798252 | |
| journal title | 2009 IEEE 15th International Symposium on High Performance Computer Architecture | |
| coverage | Academic | |
| filesize | 800767 | |
| citations | 1 |