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Memristive Circuits for LDPC Decoding

contributor authorPoikonen, J.H.
contributor authorLehtonen, E.
contributor authorLaiho, M.
contributor authorPoikonen, J.K.
date accessioned2020-03-13T00:25:40Z
date available2020-03-13T00:25:40Z
date issued2014
identifier issn2156-3357
identifier other6922162.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/1146348?locale-attribute=en&show=full
formatgeneral
languageEnglish
publisherIEEE
titleMemristive Circuits for LDPC Decoding
typeJournal Paper
contenttypeMetadata Only
identifier padid8329151
subject keywordsCMOS integrated circuits
subject keywordsintegrated circuit design
subject keywordsiterative decoding
subject keywordsmemristor circuits
subject keywordsnanowires
subject keywordsparity check codes
subject keywordsCMOL-type memristive circuits
subject keywordsLDPC code
subject keywordscellular CMOS circuit structure
subject keywordsdecoders
subject keywordsdecoding operations
subject keywordsdevice defects
subject keywordslow-density parity check codes
subject keywordsnanowire arrays
subject keywordsparity check matrix
subject keywordsprogrammable nonvolatile connectivity
subject keywordsCMOS integrated circuits
subject keywordsIterative decoding
subject keywordsMemristors
subject keywordsParity check codes
subject keywordsIterative decoding
subject keywordsmemristors
subject keywordsparity check codes
identifier doi10.1109/JETCAS.2014.2361071
journal titleEmerging and Selected Topics in Circuits and Systems, IEEE Journal on
journal volume4
journal issue4
filesize2357168
citations0


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