A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA)
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: 2014شناسه الکترونیک: 10.1109/TCAD.2014.2309859
کلیدواژه(گان): FIR filters,dynamic programming,genetic algorithms,logic design,power aware computing,switching circuits,8-tap 16-bit asynchronous QDI finite impulse response filter,CD,DCVSL,DSI,ISCAS-85 C499 circuit,MIGA,QDI,completion detection circuits,data completion detection circuit,design approach,differential cascode voltage switch logic,dynamic programming,dynamic strong indicating microcells,greedy algorithm,hardware overhead,low overhead quasi-delay-insensitive asynchronous data
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A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA)
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contributor author | Rong Zhou | |
contributor author | Kwen-Siong Chong | |
contributor author | Bah-Hwee Gwee | |
contributor author | Chang, Joseph S. | |
date accessioned | 2020-03-13T00:09:08Z | |
date available | 2020-03-13T00:09:08Z | |
date issued | 2014 | |
identifier issn | 0278-0070 | |
identifier other | 6835296.pdf | |
identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/1136260 | |
format | general | |
language | English | |
publisher | IEEE | |
title | A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA) | |
type | Journal Paper | |
contenttype | Metadata Only | |
identifier padid | 8317913 | |
subject keywords | FIR filters | |
subject keywords | dynamic programming | |
subject keywords | genetic algorithms | |
subject keywords | logic design | |
subject keywords | power aware computing | |
subject keywords | switching circuits | |
subject keywords | 8-tap 16-bit asynchronous QDI finite impulse response filter | |
subject keywords | CD | |
subject keywords | DCVSL | |
subject keywords | DSI | |
subject keywords | ISCAS-85 C499 circuit | |
subject keywords | MIGA | |
subject keywords | QDI | |
subject keywords | completion detection circuits | |
subject keywords | data completion detection circuit | |
subject keywords | design approach | |
subject keywords | differential cascode voltage switch logic | |
subject keywords | dynamic programming | |
subject keywords | dynamic strong indicating microcells | |
subject keywords | greedy algorithm | |
subject keywords | hardware overhead | |
subject keywords | low overhead quasi-delay-insensitive asynchronous data | |
identifier doi | 10.1109/TCAD.2014.2309859 | |
journal title | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on | |
journal volume | 33 | |
journal issue | 7 | |
filesize | 14644886 | |
citations | 0 |