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A Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding

contributor authorCarta, Nicola
contributor authorMeloni, Paolo
contributor authorTuveri, Giuseppe
contributor authorPani, Danilo
contributor authorRaffo, Luigi
date accessioned2020-03-12T23:58:57Z
date available2020-03-12T23:58:57Z
date issued2014
identifier issn2156-3357
identifier other6800110.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/1130254?locale-attribute=en&show=full
formatgeneral
languageEnglish
publisherIEEE
titleA Custom MPSoC Architecture With Integrated Power Management for Real-Time Neural Signal Decoding
typeJournal Paper
contenttypeMetadata Only
identifier padid8310724
subject keywordsbiotechnology
subject keywordsembedded systems
subject keywordsencoding
subject keywordsfield programmable analogue arrays
subject keywordsmechatronics
subject keywordsmedical control systems
subject keywordsmultiprocessing systems
subject keywordsneurocontrollers
subject keywordsneurophysiology
subject keywordsprosthetics
subject keywordssystem-on-chip
subject keywordsZX
subject keywordsbioengineering research
subject keywordscritical worst-case operating conditions
subject keywordscustom MPSoC architecture
subject keywordsdigital embedded system designers
subject keywordselectronic device implant
subject keywordsfield-programmable gate array-based prototype
subject keywordsintegrated power management
subject keywordsmechatronic device
subject keywordsmultiprocessor system-on-chip embedde
identifier doi10.1109/JETCAS.2014.2315881
journal titleEmerging and Selected Topics in Circuits and Systems, IEEE Journal on
journal volume4
journal issue2
filesize1344581
citations0


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