Understanding Changes in Customer Purchase Behavior: Study of Attenuation Model for Multiparametric Purchase Preferences
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: 2014DOI: 10.1109/ISVLSI.2014.94
Keyword(s): CMOS integrated circuits,n MOSFET,n SRAM chips,n cache storage,n semiconductor device models,n CMOS process,n FinCACTI,n architectural analysis,n architecture-level simulations,n cache modeling tool,n deeply-scaled FinFET devices,n robust SRAM cells,n size 7 nm,n CMOS integrated circuits,n Capacitance,n FinFETs,n Logic gates,n SRAM cells,n Semiconductor device modeling,n CACTI,n Cache Modeling,n FinFET devices
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Understanding Changes in Customer Purchase Behavior: Study of Attenuation Model for Multiparametric Purchase Preferences
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| contributor author | Cheung, Stephane | |
| contributor author | Shirai, Yasuyuki | |
| contributor author | Morita, Hiroyuki | |
| contributor author | Nakamoto, Masakazu | |
| date accessioned | 2020-03-12T22:45:30Z | |
| date available | 2020-03-12T22:45:30Z | |
| date issued | 2014 | |
| identifier other | 7022608.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/1093527?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Understanding Changes in Customer Purchase Behavior: Study of Attenuation Model for Multiparametric Purchase Preferences | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8232968 | |
| subject keywords | CMOS integrated circuits | |
| subject keywords | n MOSFET | |
| subject keywords | n SRAM chips | |
| subject keywords | n cache storage | |
| subject keywords | n semiconductor device models | |
| subject keywords | n CMOS process | |
| subject keywords | n FinCACTI | |
| subject keywords | n architectural analysis | |
| subject keywords | n architecture-level simulations | |
| subject keywords | n cache modeling tool | |
| subject keywords | n deeply-scaled FinFET devices | |
| subject keywords | n robust SRAM cells | |
| subject keywords | n size 7 nm | |
| subject keywords | n CMOS integrated circuits | |
| subject keywords | n Capacitance | |
| subject keywords | n FinFETs | |
| subject keywords | n Logic gates | |
| subject keywords | n SRAM cells | |
| subject keywords | n Semiconductor device modeling | |
| subject keywords | n CACTI | |
| subject keywords | n Cache Modeling | |
| subject keywords | n FinFET devices | |
| identifier doi | 10.1109/ISVLSI.2014.94 | |
| journal title | ata Mining Workshop (ICDMW), 2014 IEEE International Conference on | |
| filesize | 608597 | |
| citations | 0 |