Educating hardware design — From boolean equations to massively parallel computing systems
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: 2014DOI: 10.1109/NANOARCH.2014.6880481
Keyword(s): MOSFET,n SRAM chips,n circuit stability,n compensation,n integrated circuit design,n integrated circuit reliability,n negative bias temperature instability,n semiconductor device reliability,n sensors,n HSPICE simulation,n NBTI,n PTM IG-FinFET technology,n RNM,n SNM,n SRAM array Design,n adaptable trip-point sensing technique,n compensation technique,n independent gate FinFET,n negative bias temperature instability,n reliability,n self
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Educating hardware design — From boolean equations to massively parallel computing systems
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| contributor author | Knodel, Oliver | |
| contributor author | Zabel, Martin | |
| contributor author | Lehmann, Patrick | |
| contributor author | Spallek, Rainer G. | |
| date accessioned | 2020-03-12T22:18:11Z | |
| date available | 2020-03-12T22:18:11Z | |
| date issued | 2014 | |
| identifier other | 7002216.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/1078314?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Educating hardware design — From boolean equations to massively parallel computing systems | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8214605 | |
| subject keywords | MOSFET | |
| subject keywords | n SRAM chips | |
| subject keywords | n circuit stability | |
| subject keywords | n compensation | |
| subject keywords | n integrated circuit design | |
| subject keywords | n integrated circuit reliability | |
| subject keywords | n negative bias temperature instability | |
| subject keywords | n semiconductor device reliability | |
| subject keywords | n sensors | |
| subject keywords | n HSPICE simulation | |
| subject keywords | n NBTI | |
| subject keywords | n PTM IG-FinFET technology | |
| subject keywords | n RNM | |
| subject keywords | n SNM | |
| subject keywords | n SRAM array Design | |
| subject keywords | n adaptable trip-point sensing technique | |
| subject keywords | n compensation technique | |
| subject keywords | n independent gate FinFET | |
| subject keywords | n negative bias temperature instability | |
| subject keywords | n reliability | |
| subject keywords | n self | |
| identifier doi | 10.1109/NANOARCH.2014.6880481 | |
| journal title | rogrammable Logic (SPL), 2014 IX Southern Conference on | |
| filesize | 150157 | |
| citations | 0 |