Design and verification of five port router for network on chip
Publisher:
Year
: 2014DOI: 10.1109/ISQED.2014.6783339
Keyword(s): clocks,n computational complexity,n integrated circuit design,n integrated circuit interconnections,n integrated circuit modelling,n network-on-chip,n CDC cost,n CDCs,n NP-hard problem,n NoC architectures,n NoC topology generation,n SoC designs,n automated topology generation tools,n clock domain minimization,n clock-domain-crossings,n communication constraints,n interconnection architecture,n network on chip interconnect,n regular topology
Collections
:
-
Statistics
Design and verification of five port router for network on chip
Show full item record
| contributor author | Choudhari, E.M. | |
| contributor author | Dakhole, P.K. | |
| date accessioned | 2020-03-12T21:37:00Z | |
| date available | 2020-03-12T21:37:00Z | |
| date issued | 2014 | |
| identifier other | 6949913.pdf | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/1054647?locale-attribute=en | |
| format | general | |
| language | English | |
| publisher | IEEE | |
| title | Design and verification of five port router for network on chip | |
| type | Conference Paper | |
| contenttype | Metadata Only | |
| identifier padid | 8185291 | |
| subject keywords | clocks | |
| subject keywords | n computational complexity | |
| subject keywords | n integrated circuit design | |
| subject keywords | n integrated circuit interconnections | |
| subject keywords | n integrated circuit modelling | |
| subject keywords | n network-on-chip | |
| subject keywords | n CDC cost | |
| subject keywords | n CDCs | |
| subject keywords | n NP-hard problem | |
| subject keywords | n NoC architectures | |
| subject keywords | n NoC topology generation | |
| subject keywords | n SoC designs | |
| subject keywords | n automated topology generation tools | |
| subject keywords | n clock domain minimization | |
| subject keywords | n clock-domain-crossings | |
| subject keywords | n communication constraints | |
| subject keywords | n interconnection architecture | |
| subject keywords | n network on chip interconnect | |
| subject keywords | n regular topology | |
| identifier doi | 10.1109/ISQED.2014.6783339 | |
| journal title | ommunications and Signal Processing (ICCSP), 2014 International Conference on | |
| filesize | 1785147 | |
| citations | 0 |