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نمایش تعداد 1-5 از 5

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS

نوع: Journal Paper

نویسنده : Borremans, J.; Ryckaert, J.; Desset, C.; Kuijk, M.; Wambacq, P.; Craninckx, J.

سال: 2009

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A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

نوع: Journal Paper

نویسنده : Ryckaert, J.; Van der Plas, G.; De Heyn, V.; Desset, C.; Van Poucke, B.; Craninckx, J.

سال: 2007

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ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy

نوع: Conference Paper

نویسنده : Kumar Rethinagiri, S.; Palomar, O.; Sobe, A.; Knauth, T.; Barczynski, W.; Yalcin, G.; Hayduk, Y.; Cristal, A.; Unsal, O.; Felber, P.; Fetzer, C.; Ryckaert, J.; Alioto, G.

ناشر: IEEE

سال: 2014

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

نوع: Conference Paper

نویسنده : Bao, T.H.; Yakimets, D.; Ryckaert, J.; Ciofi, I.; Baert, R.; Veloso, A.; Boemmels, J.; Collaert, N.; Roussel, P.; Demuynck, S.; Raghavan, P.; Mercha, A.; Tokei, Z.; Verkest, D.; Thean, A.V.-Y.; Wambacq, P.

ناشر: IEEE

سال: 2014

Design Technology co-optimization for N10

نوع: Conference Paper

نویسنده : Ryckaert, J.; Raghavan, P.; Baert, R.; Bardon, M.G.; Dusa, M.; Mallik, A.; Sakhare, S.; Vandewalle, B.; Wambacq, P.; Chava, B.; Croes, K.; Dehan, M.; Jang, D.; Leray, P.; Liu, T.-T.; Miyaguchi, K.; Parvais, B.; Schuddinck, P.; Weemaes, P.; Mercha, A.; Bommels, J.; Horiguchi, N.; McIntyre, G.; Thean, A.; Tokei, Z.; Cheng, S.; Verkest, D.; Steegen, A.

ناشر: IEEE

سال: 2014

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A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

Design Technology co-optimization for N10

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A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

Design Technology co-optimization for N10