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RISDigital Background Calibration of Capacitor Mismatch Errors in Pipelined ADCs
A digital background calibration technique is proposed to correct for the linearity error due to capacitor mismatches in pipelined analog-to-digital converters (ADCs). During the normal ADC operation, it randomly swaps the ...
Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs
Digital calibration techniques are widely utilized to linearize pipelined analog-to-digital converters (ADCs). However, their power dissipation can be prohibitively high, particularly when high-order gain calibration is ...
A Reconfigurable and Power-Scalable 10-12 bit 0.4-44 MS/s Pipelined ADC with 0.35-0.5 pJ/step in 1.2 V 90 nm Digital CMOS
A pipelined ADC, reconfigurable over bandwidths of 0.2-22 MHz (sampling frequencies of 0.4-44 MS/s) and resolutions of 10-12 bits, is described for applications in multi-standard wireless terminals. Fabricated in a 1.2-V ...
A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp with Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS
A pseudo-cascode compensation technique is proposed to enable a process-insensitive and current-scalable design of the classical two-stage opamp at low supply voltages, without requiring any additional power dissipation. ...