Search

نمایش تعداد 1-10 از 52

Variation-Aware Variable Latency Design

نوع: Journal Paper

نویسنده : Gupta, Swastik; Sapatnekar, Sachin S.

ناشر: IEEE

سال: 2014

A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter

نوع: Journal Paper

نویسنده : Bongjin Kim; Weichao Xu; Kim, Chul Han

ناشر: IEEE

سال: 2014

Variability Modeling and Process Optimization for the 32 nm BEOL Using In-Line Scatterometry Data

نوع: Journal Paper

نویسنده : Faruk, M. Golam; Angyal, Matthew S.; Ogunsola, Oluwafemi; Watts, David K.; Wilkins, Richard

ناشر: IEEE

سال: 2014

Constraint-based platform variants specification for early system verification

نوع: Conference Paper

ناشر: IEEE

سال: 2014

Optimal dimensioning of active cell balancing architectures

نوع: Conference Paper

ناشر: IEEE

سال: 2014

An efficient reliable PUF-based cryptographic key generator in 65nm CMOS

نوع: Conference Paper

نویسنده : Bhargava, M. , Mai, K.

ناشر: IEEE

سال: 2014

Application of optimization method for optimal control of the steelmaking process

نوع: Conference Paper

نویسنده : Laciak, M. , Kacur, J. , Durdan, M. , Flegner, P.

ناشر: IEEE

سال: 2014

Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing

نوع: Journal Paper

نویسنده : Yang Lu; Lombardi, Floriana; Pontarelli, Salvatore; Ottavi, Marco

ناشر: IEEE

سال: 2014

Measuring propagation delays of critical paths using time-resolved LADA

نوع: Conference Paper

ناشر: IEEE

سال: 2014

A Dynamic User Interface for Transit Tracking Applications

نوع: Conference Paper

نویسنده : Gelowitz, Craig M. , Paranjape, Raman

ناشر: IEEE

سال: 2014

1
2
3
4
. . .
6

Search

Variation-Aware Variable Latency Design

A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter

Variability Modeling and Process Optimization for the 32 nm BEOL Using In-Line Scatterometry Data

Constraint-based platform variants specification for early system verification

Optimal dimensioning of active cell balancing architectures

An efficient reliable PUF-based cryptographic key generator in 65nm CMOS

Application of optimization method for optimal control of the steelmaking process

Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing

Measuring propagation delays of critical paths using time-resolved LADA

A Dynamic User Interface for Transit Tracking Applications

نویسنده

ناشر

سال

کلیدواژه

نوع

زبان

نوع محتوا

عنوان ناشر

Search

Filters

Variation-Aware Variable Latency Design

A Supply-Noise Sensitivity Tracking PLL in 32 nm SOI Featuring a Deep Trench Capacitor Based Loop Filter

Variability Modeling and Process Optimization for the 32 nm BEOL Using In-Line Scatterometry Data

Constraint-based platform variants specification for early system verification

Optimal dimensioning of active cell balancing architectures

An efficient reliable PUF-based cryptographic key generator in 65nm CMOS

Application of optimization method for optimal control of the steelmaking process

Design and Analysis of Single-Event Tolerant Slave Latches for Enhanced Scan Delay Testing

Measuring propagation delays of critical paths using time-resolved LADA

A Dynamic User Interface for Transit Tracking Applications