In this paper several low power full adder topologies are

presented. The main idea of these circuits is based on the sense energy

recovery full adder (SERF) design and the GDI (Gate diffusion input)

technique. These subthreshold...

This paper presents a power-efficient voltage level-shifter architecture capable of converting extremely low levels of input voltages to higher levels. In order to avoid the static power dissipation, the proposed structure ...

In this paper a new full adder (FA) circuit optimized for ultra low power operation is proposed. The

circuit is based on modified XOR gates operated in the subthreshold region to minimize the power consumption. Simulated results using 65nm...

In this paper challenges observed in 65nm technology for

circuits utilizing subthreshold region operation are presented.

Different circuits are analyzed and simulated for ultra low

supply voltages to find the best topology...

This brief presents a fast and power-efficient voltage level-shifting circuit capable of converting extremely low levels of input voltages into high output voltage levels. The efficiency of the proposed circuit is ...

Abstract— Designing logic circuits in the subthreshold regime is

one of the most effective ways to reduce the power consumption

of digital circuits. In the subthreshold region, the current is an

exponential function...

In this paper, a low-power voltage level shifter is proposed which is able to convert sub-threshold voltage levels of input signal to above-threshold voltage levels. The proposed circuit is based on a modified Wilson current mirror structure which...