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A Layout-Level Approach to Evaluate and Mitigate the Sensitive Areas of Multiple SETs in Combinational Circuits

Type: Journal Paper

Author : Yankang Du; Shuming Chen; Jianjun Jianjun

Publisher: IEEE

Year: 2014

A Constrained Layout Placement Approach to Enhance Pulse Quenching Effect in Large Combinational Circuits

Type: Journal Paper

Author : Yankang Du; Shuming Chen; Biwei Liu

Publisher: IEEE

Year: 2014

Calculating the Soft Error Vulnerabilities of Combinational Circuits by Re-Considering the Sensitive Area

Type: Journal Paper

Author : Shuming Chen; Yankang Du; Biwei Liu; Junrui Qin

Publisher: IEEE

Year: 2014

Simulation Study of the Single-Event Effects Sensitivity in Nanoscale CMOS for Body-Biasing Circuits

Type: Journal Paper

Author : Junrui Qin; Shuming Chen; Changguo Guo; Yankang Du

Publisher: IEEE

Year: 2014

Voltage Dependency of Propagating Single-Event Transient Pulsewidths in 90-nm CMOS Technology

Type: Journal Paper

Author : Junrui Qin; Shuming Chen; Bin Liang; Zhen Ge; Yibai He; Yankang Du; Biwei Liu; Jianjun Chen; Dawei Li

Year: 2014

Author

Shuming Chen (5)

Yankang Du (5)

Biwei Liu (3)

Junrui Qin (3)

Bin Liang (1)

Changguo Guo (1)

Dawei Li (1)

Jianjun Chen (1)

Jianjun Jianjun (1)

Yibai He (1)

Publisher

IEEE (4)

Year

2014 (5)

Keywords

combinational circuits (3)

Layout (3)

MOSFET (3)

radiation hardening (electronics) (3)

Combinational circuits (2)

integrated circuit layout (2)

Ions (2)

Logic gates (2)

Body-biasing (1)

body-biasing circuits (1)

Type

Journal Paper (5)

Language (ISO)

English (5)

Content Type

Metadata Only (4)

Fulltext (1)

Publication Title

Device and Materials Reliability, IEEE Transactions on (3)

IEEE Transactions on Device and Materials Reliability (1)

Nuclear Science, IEEE Transactions on (1)

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