Search

Now showing items 1-3 of 3

Silicon nitride stop layer in back-end-of-line planarization for wafer bonding application

Type: Conference Paper

Author : Lisker, M.; Trusch, A.; Kruger, A.; Fraschke, M.; Tillack, B.; Weimann, N.; Ostermay, I.; Kruger, O.

Publisher: IEEE

Year: 2014

About the application of CMP for Monolithic integration of photonic components in a 0.25 μm BiCMOS process

Type: Conference Paper

Author : Trusch, A.; Lisker, M.; Yamamoto, Y.; Kruger, A.; Lischke, S.; Knoll, D.; Tillack, B.

Publisher: IEEE

Year: 2014

SiGe p-n-p HBTs With 265-GHz f<sub>max</sub>, 175-GHz f<sub>T</sub>, and 3.65-ps Gate Delay

Type: Journal Paper

Author : Heinemann, B.; Rucker, Holger; Barth, R.; Drews, J.; Fursenko, O.; Grabolla, T.; Kurps, R.; Marschmeyer, S.; Scheit, A.; Schmidt, Dan; Trusch, A.; Wolansky, Dirk; Yamamoto, Yusaku

Publisher: IEEE

Year: 2014

Search

Silicon nitride stop layer in back-end-of-line planarization for wafer bonding application

About the application of CMP for Monolithic integration of photonic components in a 0.25 μm BiCMOS process

SiGe p-n-p HBTs With 265-GHz f<sub>max</sub>, 175-GHz f<sub>T</sub>, and 3.65-ps Gate Delay

Author

Publisher

Year

Keywords

Type

Language (ISO)

Content Type

Publication Title

Search

Filters

Silicon nitride stop layer in back-end-of-line planarization for wafer bonding application

About the application of CMP for Monolithic integration of photonic components in a 0.25 &#x03BC;m BiCMOS process

SiGe p-n-p HBTs With 265-GHz f<sub>max</sub>, 175-GHz f<sub>T</sub>, and 3.65-ps Gate Delay

About the application of CMP for Monolithic integration of photonic components in a 0.25 μm BiCMOS process