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Now showing items 1-10 of 13

A Novel Dual-Core Architecture for the Analysis of DNA Microarray Images

Type: Journal Paper

Author : Sterpone, L.

Year: 2009

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A new reliability-oriented place and route algorithm for SRAM-based FPGAs

Type: Journal Paper

Author : Sterpone, L.; Violante, M.

Year: 2006

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Analysis and mitigation of single event effects on flash-based FPGAS

Type: Conference Paper

Author : Sterpone, L. , Boyang Du

Publisher: IEEE

Year: 2014

A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs

Type: Journal Paper

Author : Sterpone, L.; Violante, M.

Year: 2005

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On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors

Type: Journal Paper

Author : Sabena, D.; Reorda, M. Sonza; Sterpone, L.

Publisher: IEEE

Year: 2014

Soft error effects analysis and mitigation in VLIW safety-critical applications

Type: Conference Paper

Author : Sabena, D.; Reorda, M.Sonza; Sterpone, L.

Publisher: IEEE

Year: 2014

Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation

Type: Conference Paper

Author : Alexandrescu, D. , Sterpone, L. , Lopez-Ongil, C.

Publisher: IEEE

Year: 2014

Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs

Type: Conference Paper

Author : Sanchez, E.; Sterpone, L.; Ullah, A.

Publisher: IEEE

Year: 2014

Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs

Type: Conference Paper

Author : Desogus, M. , Sterpone, L. , Codinachs, D.M.

Publisher: IEEE

Year: 2014

[IEEE Comput. Soc 10th IEEE International On-Line Testing Symposium - Funchal, Madeira Island, Portugal (12-14 July 2004)] Proceedings. 10th IEEE International On-Line Testing Symposium - On the evaluation of SEU sensitiveness in SRAM-based FPGAs

Type: Journal Paper

Author : Bernardi, P.; Reorda, M.S.; Sterpone, L.; Violante, M.

Year: 2004

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A Novel Dual-Core Architecture for the Analysis of DNA Microarray Images

A new reliability-oriented place and route algorithm for SRAM-based FPGAs

Analysis and mitigation of single event effects on flash-based FPGAS

A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs

On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors

Soft error effects analysis and mitigation in VLIW safety-critical applications

Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation

Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs

Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs

[IEEE Comput. Soc 10th IEEE International On-Line Testing Symposium - Funchal, Madeira Island, Portugal (12-14 July 2004)] Proceedings. 10th IEEE International On-Line Testing Symposium - On the evaluation of SEU sensitiveness in SRAM-based FPGAs

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A Novel Dual-Core Architecture for the Analysis of DNA Microarray Images

A new reliability-oriented place and route algorithm for SRAM-based FPGAs

Analysis and mitigation of single event effects on flash-based FPGAS

A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs

On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors

Soft error effects analysis and mitigation in VLIW safety-critical applications

Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation

Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs

Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs

[IEEE Comput. Soc 10th IEEE International On-Line Testing Symposium - Funchal, Madeira Island, Portugal (12-14 July 2004)] Proceedings. 10th IEEE International On-Line Testing Symposium - On the evaluation of SEU sensitiveness in SRAM-based FPGAs