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Hyper threading-aware Virtual Machine migration

Type: Conference Paper

Author : Oh, Chungmu , Ro, Won Woo

Publisher: IEEE

Year: 2014

Exploiting Implementation Diversity and Partial Connection of Routers in Application-Specific Network-on-Chip Topology Synthesis

Type: Journal Paper

Author : Minje Jun; Ro, Won Woo; Eui-Young Chung

Publisher: IEEE

Year: 2014

Development of efficient VCPU pinning mechanism in Xen

Type: Conference Paper

Author : Min, Kyung Yoon , Kim, Seung Hun , Ro, Won Woo

Publisher: IEEE

Year: 2014

Multicore speedup models using frequency scaling with fixed power budget

Type: Conference Paper

Author : Lee, Seungwon , Kim, Seung Hun , Ro, Won Woo

Publisher: IEEE

Year: 2014

Accelerating MapReduce framework on multi-GPU systems

Type: Journal Paper

Author : Jiang, Hai; Chen, Yi; Qiao, Zhi; Li, Kuan-Ching; Ro, WonWoo; Gaudiot, Jean-Luc

Publisher: Springer

Year: 2013

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Accelerating gesture recognition algorithm using coarse grained reconfigurable architectures

Type: Conference Paper

Author : Kim, Minsik; Kim, Deokho; Sung, Minyong; Lee, Wonjae; Kim, Jaehyun; Ro, Won Woo

Publisher: IEEE

Year: 2014

LUT based secure cloud computing — An implementation using FPGAs

Type: Conference Paper

Author : Xu, Lei; Khoa, Pham Dang; Kim, Seung Hun; Ro, Won Woo; Shi, Weidong

Publisher: IEEE

Year: 2014

C-Lock: Energy Efficient Synchronization for Embedded Multicore Systems

Type: Journal Paper

Author : Kim, Seung Hun; Lee, Sang Hyong; Jun, Minje; Lee, Byunghoon; Ro, Won Woo; Chung, Eui-Young; Gaudiot, Jean-Luc

Publisher: IEEE

Year: 2013

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Hyper threading-aware Virtual Machine migration

Exploiting Implementation Diversity and Partial Connection of Routers in Application-Specific Network-on-Chip Topology Synthesis

Development of efficient VCPU pinning mechanism in Xen

Multicore speedup models using frequency scaling with fixed power budget

Accelerating MapReduce framework on multi-GPU systems

Accelerating gesture recognition algorithm using coarse grained reconfigurable architectures

LUT based secure cloud computing — An implementation using FPGAs

C-Lock: Energy Efficient Synchronization for Embedded Multicore Systems

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Hyper threading-aware Virtual Machine migration

Exploiting Implementation Diversity and Partial Connection of Routers in Application-Specific Network-on-Chip Topology Synthesis

Development of efficient VCPU pinning mechanism in Xen

Multicore speedup models using frequency scaling with fixed power budget

Accelerating MapReduce framework on multi-GPU systems

Accelerating gesture recognition algorithm using coarse grained reconfigurable architectures

LUT based secure cloud computing &#x2014; An implementation using FPGAs

C-Lock: Energy Efficient Synchronization for Embedded Multicore Systems

LUT based secure cloud computing — An implementation using FPGAs