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A simulation study of self-heating effect on junctionless nanowire transistors

Type: Conference Paper

Author : Mariniello, G.; Pavanello, M.A.

Publisher: IEEE

Year: 2014

Improved continuous model for short channel double-gate junctionless transistors

Type: Conference Paper

Author : Cardoso Paz, B.; Avila, F.; Cerdeira, A.; Pavanello, M.A.

Publisher: IEEE

Year: 2014

Dependence of the optimum length of light doped region of GC SOI nMOSFET with front gate bias

Type: Conference Paper

Author : Assalti, R.; Pavanello, M.A.; Flandre, D.; de Souza, M.

Publisher: IEEE

Year: 2014

Short channel continuous model for double-gate junctionless transistors

Type: Conference Paper

Author : Cardoso Paz, B.; Pavanello, M.A.; Avila, F.; Cerdeira, A.

Publisher: IEEE

Year: 2014

Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors

Type: Conference Paper

Author : Assalti, R.; Pavanello, M.A.; de Souza, M.; Flandre, D.

Publisher: IEEE

Year: 2014

Effective mobility analysis of n- and p-types SOI junctionless nanowire transistors

Type: Conference Paper

Author : Doria, R.T.; Trevisoli, R.; de Souza, M.; Pavanello, M.A.

Publisher: IEEE

Year: 2014

Effect of the temperature on on Junctionless Nanowire Transistors electrical parameters down to 4K

Type: Conference Paper

Author : Trevisoli, R.; de Souza, M.; Doria, R.T.; Kilchtyska, V.; Flandre, D.; Pavanello, M.A.

Publisher: IEEE

Year: 2014

Analog performance of short-channel asymmetric self-cascode of junctionless nanowire nMOS transistors

Type: Conference Paper

Author : de Souza, M.; Doria, R.T.; Trevisoli, R.; Pavanello, M.A.

Publisher: IEEE

Year: 2014

Junctionless Multiple-Gate Transistors for Analog Applications

Type: Journal Paper

Author : Doria, R.T.; Pavanello, M.A.; Trevisoli, R.D.; de Souza, M.; Chi-Woo Lee; Ferain, I.; Akhavan, N.D.; Ran Yan; Razavi, P.; Ran Yu; Kranti, A.; Colinge, J.

Year: 2011

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A simulation study of self-heating effect on junctionless nanowire transistors

Improved continuous model for short channel double-gate junctionless transistors

Dependence of the optimum length of light doped region of GC SOI nMOSFET with front gate bias

Short channel continuous model for double-gate junctionless transistors

Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors

Effective mobility analysis of n- and p-types SOI junctionless nanowire transistors

Effect of the temperature on on Junctionless Nanowire Transistors electrical parameters down to 4K

Analog performance of short-channel asymmetric self-cascode of junctionless nanowire nMOS transistors

Junctionless Multiple-Gate Transistors for Analog Applications

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A simulation study of self-heating effect on junctionless nanowire transistors

Improved continuous model for short channel double-gate junctionless transistors

Dependence of the optimum length of light doped region of GC SOI nMOSFET with front gate bias

Short channel continuous model for double-gate junctionless transistors

Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors

Effective mobility analysis of n- and p-types SOI junctionless nanowire transistors

Effect of the temperature on on Junctionless Nanowire Transistors electrical parameters down to 4K

Analog performance of short-channel asymmetric self-cascode of junctionless nanowire nMOS transistors

Junctionless Multiple-Gate Transistors for Analog Applications