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Now showing items 1-10 of 13

A systematic approach for design of digit-serial signal processing architectures

Type: Journal Paper

Author : Parhi, K.K.

Year: 1991

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High-speed VLSI architectures for the AES algorithm

Type: Journal Paper

Author : Xinmiao Zhang,; Parhi, K.K.

Year: 2004

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Interleaved successive cancellation polar decoders

Type: Conference Paper

Author : Chuan Zhang , Parhi, K.K.

Publisher: IEEE

Year: 2014

Architectures for IIR digital filters using stochastic computing

Type: Conference Paper

Author : Parhi, K.K. , Yin Liu

Publisher: IEEE

Year: 2014

Protecting DSP circuits through obfuscation

Type: Conference Paper

Author : Yingjie Lao , Parhi, K.K.

Publisher: IEEE

Year: 2014

Architectures for polar BP decoders using folding

Type: Conference Paper

Author : Bo Yuan , Parhi, K.K.

Publisher: IEEE

Year: 2014

Seizure detection using wavelet decomposition of the prediction error signal from a single channel of intra-cranial EEG

Type: Conference Paper

Author : Zisheng Zhang; Parhi, K.K.

Publisher: IEEE

Year: 2014

[IEEE Conference Record. Thirty-Fifth Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, USA (2001.11.4-2001.11.7)] Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256) - Low-power 4-2 and 5-2 compressors

Type: Journal Paper

Author : Prasad, K.; Parhi, K.K.

Year: 2001

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A fast VLSI adder architecture

Type: Journal Paper

Author : Srinivas, H.R.; Parhi, K.K.

Year: 1992

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Pulsed-OFDM Modulation for Ultrawideband Communications

Type: Journal Paper

Author : Saberinia, E.; Tang, J.; Tewfik, A.H.; Parhi, K.K.

Year: 2009

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A systematic approach for design of digit-serial signal processing architectures

High-speed VLSI architectures for the AES algorithm

Interleaved successive cancellation polar decoders

Architectures for IIR digital filters using stochastic computing

Protecting DSP circuits through obfuscation

Architectures for polar BP decoders using folding

Seizure detection using wavelet decomposition of the prediction error signal from a single channel of intra-cranial EEG

[IEEE Conference Record. Thirty-Fifth Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, USA (2001.11.4-2001.11.7)] Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256) - Low-power 4-2 and 5-2 compressors

A fast VLSI adder architecture

Pulsed-OFDM Modulation for Ultrawideband Communications

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A systematic approach for design of digit-serial signal processing architectures

High-speed VLSI architectures for the AES algorithm

Interleaved successive cancellation polar decoders

Architectures for IIR digital filters using stochastic computing

Protecting DSP circuits through obfuscation

Architectures for polar BP decoders using folding

Seizure detection using wavelet decomposition of the prediction error signal from a single channel of intra-cranial EEG

[IEEE Conference Record. Thirty-Fifth Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, USA (2001.11.4-2001.11.7)] Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256) - Low-power 4-2 and 5-2 compressors

A fast VLSI adder architecture

Pulsed-OFDM Modulation for Ultrawideband Communications