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Now showing items 1-6 of 6

VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications

Type: Journal Paper

Author : Jangwon Park; Jongsun Park; Bhunia, Swarup

Publisher: IEEE

Year: 2014

A low-complexity composite QR decomposition architecture for MIMO detector

Type: Conference Paper

Author : Ji-Hwan Yoon , Dongyeob Shin , Jongsun Park

Publisher: IEEE

Year: 2014

An Adaptive Impedance-Matching Network Based on a Novel Capacitor Matrix for Wireless Power Transfer

Type: Journal Paper

Author : Yongseok Lim; Hoyoung Tang; Seungok Lim; Jongsun Park

Publisher: IEEE

Year: 2014

Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority

Type: Journal Paper

Author : Min-Woo Lee; Ji-Hwan Yoon; Jongsun Park

Publisher: IEEE

Year: 2014

A 0.4-mW, 4.7-ps Resolution Single-Loop ΔΣ TDC Using a Half-Delay Time Integrator

Type: Journal Paper

Author : Chan-Keun Kwon; Hoonki Kim; Jongsun Park; Soo-Won Kim

Year: 2015

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[IEEE Proceedings of the International Symposium on Low Power Electronics and Design - Monterey, CA, USA (2002.08.14-2002.08.14)] Proceedings of the International Symposium on Low Power Electronics and Design - High performance and low power FIR filter design based on sharing multiplication

Type: Journal Paper

Author : Jongsun Park,; Woopyo Jeong,; Hunsoo Choo,; Mahmoodi-Meimand, H.; Yongtao Wang,; Roy, K.

Year: 2002

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VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications

A low-complexity composite QR decomposition architecture for MIMO detector

An Adaptive Impedance-Matching Network Based on a Novel Capacitor Matrix for Wireless Power Transfer

Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority

A 0.4-mW, 4.7-ps Resolution Single-Loop ΔΣ TDC Using a Half-Delay Time Integrator

[IEEE Proceedings of the International Symposium on Low Power Electronics and Design - Monterey, CA, USA (2002.08.14-2002.08.14)] Proceedings of the International Symposium on Low Power Electronics and Design - High performance and low power FIR filter design based on sharing multiplication

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VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications

A low-complexity composite QR decomposition architecture for MIMO detector

An Adaptive Impedance-Matching Network Based on a Novel Capacitor Matrix for Wireless Power Transfer

Reconfigurable CORDIC-Based Low-Power DCT Architecture Based on Data Priority

A 0.4-mW, 4.7-ps Resolution Single-Loop ΔΣ TDC Using a Half-Delay Time Integrator

[IEEE Proceedings of the International Symposium on Low Power Electronics and Design - Monterey, CA, USA (2002.08.14-2002.08.14)] Proceedings of the International Symposium on Low Power Electronics and Design - High performance and low power FIR filter design based on sharing multiplication