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Now showing items 1-9 of 9

High-performance and low-power memory-interface architecture for video processing applications

Type: Journal Paper

Author : Hansoo Kim; In-Cheol Park

Year: 2001

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Single-step glitch-free NAND-based digitally controlled delay lines using dual loops

Type: Journal Paper

Author : Youngjoo Lee; In-Cheol Park

Publisher: IET

Year: 2014

[IEEE 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008 - Seattle, WA, USA (2008.05.18-2008.05.21)] 2008 IEEE International Symposium on Circuits and Systems - Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters

Type: Journal Paper

Author : Jeong-Sup Lee,; In-Cheol Park,

Year: 2008

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7.3 Gb/s universal BCH encoder and decoder for SSD controllers

Type: Conference Paper

Author : Hoyoung Yoo , Youngjoo Lee , In-Cheol Park

Publisher: IEEE

Year: 2014

Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters

Type: Journal Paper

Author : YoungJoo Lee; In-Cheol Park

Year: 2010

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Area-efficient method to approximate two minima for LDPC decoders

Type: Journal Paper

Author : Jaehwan Jung; Youngjoo Lee; In-Cheol Park

Publisher: IET

Year: 2014

Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders

Type: Journal Paper

Author : Injae Yoo; Bongjin Kim; In-Cheol Park

Publisher: IEEE

Year: 2014

High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives

Type: Journal Paper

Author : Youngjoo Lee; Hoyoung Yoo; Injae Yoo; In-Cheol Park

Publisher: IEEE

Year: 2014

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes

Type: Journal Paper

Author : Byeong Yong Kong; Jihyuck Jo; Hyewon Jeong; Mina Hwang; Soyoung Cha; Bongjin Kim; In-Cheol Park

Publisher: IEEE

Year: 2014

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High-performance and low-power memory-interface architecture for video processing applications

Single-step glitch-free NAND-based digitally controlled delay lines using dual loops

[IEEE 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008 - Seattle, WA, USA (2008.05.18-2008.05.21)] 2008 IEEE International Symposium on Circuits and Systems - Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters

7.3 Gb/s universal BCH encoder and decoder for SSD controllers

Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters

Area-efficient method to approximate two minima for LDPC decoders

Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders

High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes

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High-performance and low-power memory-interface architecture for video processing applications

Single-step glitch-free NAND-based digitally controlled delay lines using dual loops

[IEEE 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008 - Seattle, WA, USA (2008.05.18-2008.05.21)] 2008 IEEE International Symposium on Circuits and Systems - Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters

7.3 Gb/s universal BCH encoder and decoder for SSD controllers

Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters

Area-efficient method to approximate two minima for LDPC decoders

Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders

High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives

Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes