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Now showing items 1-9 of 9
Single-step glitch-free NAND-based digitally controlled delay lines using dual loops
Publisher: IET
Year: 2014
7.3 Gb/s universal BCH encoder and decoder for SSD controllers
Publisher: IEEE
Year: 2014
Area-efficient method to approximate two minima for LDPC decoders
Publisher: IET
Year: 2014
Tail-Overlapped SISO Decoding for High-Throughput LTE-Advanced Turbo Decoders
Publisher: IEEE
Year: 2014
High-Throughput and Low-Complexity BCH Decoding Architecture for Solid-State Drives
Publisher: IEEE
Year: 2014