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Shortest path reduction in a class of uniform fault tolerant networks

Type: Conference Paper

Author : Joshi, Prashant D.; Hamdioui, Said

Publisher: IEEE

Year: 2014

Layout-Based Refined NPSF Model for DRAM Characterization and Testing

Type: Journal Paper

Author : Sfikas, Yiorgos; Tsiatouhas, Yiorgos E.; Hamdioui, Said

Publisher: IEEE

Year: 2014

Region Disjoint Paths in a Class of Optimal Line Graph Networks

Type: Conference Paper

Author : Joshi, Prashant D.; Sen, Arunabha; Hamdioui, Said; Bertels, Koen

Publisher: IEEE

Year: 2014

Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface

Type: Conference Paper

Author : Marinissen, Erik Jan; De Wachter, Bart; Smith, Ken; Kiesewetter, Jorg; Taouil, Mottaqiallah; Hamdioui, Said

Publisher: IEEE

Year: 2014

Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates

Type: Journal Paper

Author : Kukner, Halil; Khan, Sharifullah; Weckx, Pieter; Raghavan, Praveen; Hamdioui, Said; Kaczer, Ben; Catthoor, Francky; Van der Perre, Liesbet; Lauwereins, Rudy; Groeseneken, Guido

Publisher: IEEE

Year: 2014

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Shortest path reduction in a class of uniform fault tolerant networks

Layout-Based Refined NPSF Model for DRAM Characterization and Testing

Region Disjoint Paths in a Class of Optimal Line Graph Networks

Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface

Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates

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Shortest path reduction in a class of uniform fault tolerant networks

Layout-Based Refined NPSF Model for DRAM Characterization and Testing

Region Disjoint Paths in a Class of Optimal Line Graph Networks

Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface

Comparison of Reaction-Diffusion and Atomistic Trap-Based BTI Models for Logic Gates