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A high parallel way for processing IQ/IT part of HEVC decoder based on GPU

Type: Conference Paper

Author : He, Lang-ping; Goto, Satoshi

Publisher: IEEE

Year: 2014

[IEEE 2012 IEEE International Conference on Multimedia and Expo (ICME) - Melbourne, Australia (2012.07.9-2012.07.13)] 2012 IEEE International Conference on Multimedia and Expo - A Low-Complexity HEVC Intra Prediction Algorithm Based on Level and Mode Filtering

Type: Journal Paper

Author : Sun, Heming; Zhou, Dajiang; Goto, Satoshi

Year: 2012

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OpenCL based high-quality HEVC motion estimation on GPU

Type: Conference Paper

Author : Wang, Fan; Zhou, Dajiang; Goto, Satoshi

Publisher: IEEE

Year: 2014

Non-Redundant Gradient Semantic Local Binary Patterns for pedestrian detection

Type: Conference Paper

Author : Xu, Jiu; Jiang, Ning; Goto, Satoshi

Publisher: IEEE

Year: 2014

Live demonstration: FPGA based 3840×2160 video decoding and displaying system

Type: Conference Paper

Author : Zhang, Haoming; Zhou, Dajiang; Goto, Satoshi

Publisher: IEEE

Year: 2014

A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec

Type: Journal Paper

Author : Li Guo; Dajiang Zhou; Goto, Satoshi

Publisher: IEEE

Year: 2014

A 1.59 Gpixel/s Motion Estimation Processor With <formula formulatype="inline"> <img src="/images/tex/277.gif" alt="-"> </formula>211 to +211 Search Range for UHDTV Video Encoder

Type: Journal Paper

Author : Dajiang Zhou; Jinjia Zhou; Gang He; Goto, Satoshi

Publisher: IEEE

Year: 2014

A low power 720p motion estimation processor with 3D stacked memory

Type: Conference Paper

Author : Zhang, Shuping; Zhou, Jinjia; Zhou, Dajiang; Goto, Satoshi

Publisher: IEEE

Year: 2014

Reducing power consumption of HEVC codec with lossless reference frame recompression

Type: Conference Paper

Author : Zhou, Dajiang; Guo, Li; Zhou, Jinjia; Goto, Satoshi

Publisher: IEEE

Year: 2014

VLSI architecture of HEVC intra prediction for 8K UHDTV applications

Type: Conference Paper

Author : Zhou, Jianbin; Zhou, Dajiang; Sun, Heming; Goto, Satoshi

Publisher: IEEE

Year: 2014

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A high parallel way for processing IQ/IT part of HEVC decoder based on GPU

[IEEE 2012 IEEE International Conference on Multimedia and Expo (ICME) - Melbourne, Australia (2012.07.9-2012.07.13)] 2012 IEEE International Conference on Multimedia and Expo - A Low-Complexity HEVC Intra Prediction Algorithm Based on Level and Mode Filtering

OpenCL based high-quality HEVC motion estimation on GPU

Non-Redundant Gradient Semantic Local Binary Patterns for pedestrian detection

Live demonstration: FPGA based 3840×2160 video decoding and displaying system

A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec

A 1.59 Gpixel/s Motion Estimation Processor With <formula formulatype="inline"> <img src="/images/tex/277.gif" alt="-"> </formula>211 to +211 Search Range for UHDTV Video Encoder

A low power 720p motion estimation processor with 3D stacked memory

Reducing power consumption of HEVC codec with lossless reference frame recompression

VLSI architecture of HEVC intra prediction for 8K UHDTV applications

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A high parallel way for processing IQ/IT part of HEVC decoder based on GPU

[IEEE 2012 IEEE International Conference on Multimedia and Expo (ICME) - Melbourne, Australia (2012.07.9-2012.07.13)] 2012 IEEE International Conference on Multimedia and Expo - A Low-Complexity HEVC Intra Prediction Algorithm Based on Level and Mode Filtering

OpenCL based high-quality HEVC motion estimation on GPU

Non-Redundant Gradient Semantic Local Binary Patterns for pedestrian detection

Live demonstration: FPGA based 3840&#x00D7;2160 video decoding and displaying system

A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec

A 1.59 Gpixel/s Motion Estimation Processor With <formula formulatype="inline"> <img src="/images/tex/277.gif" alt="-"> </formula>211 to +211 Search Range for UHDTV Video Encoder

A low power 720p motion estimation processor with 3D stacked memory

Reducing power consumption of HEVC codec with lossless reference frame recompression

VLSI architecture of HEVC intra prediction for 8K UHDTV applications

Live demonstration: FPGA based 3840×2160 video decoding and displaying system