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A 0.8–4-GHz Software-Defined Radio Receiver With Improved Harmonic Rejection Through Non-Overlapped Clocking
Year: 2018
Abstract:
The RF section of a software-defined-radio receiver front-end with harmonic rejection is presented. The proposed mixer-based receiver provides two programmable notches that can be located in any desired frequencies, e.g., ...
A 350-MS/s Continuous-Time Delta–Sigma Modulator With a Digitally Assisted Binary-DAC and a 5-Bits Two-Step-ADC Quantizer in 130-nm CMOS
Year: 2015
Abstract:
Two techniques to improve the performance of continuous-time delta–sigma (CTDS) modulators are presented. A digital calibration technique is introduced to enable the use of binary current digital-to-analog converters (DACs) ...