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A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

Type: Journal Paper

Author : Silveira, F.; Flandre, D.; Jespers, P.G.A.

Year: 1996

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Dependence of the optimum length of light doped region of GC SOI nMOSFET with front gate bias

Type: Conference Paper

Author : Assalti, R.; Pavanello, M.A.; Flandre, D.; de Souza, M.

Publisher: IEEE

Year: 2014

Efficient ultra low power rectification at 13.56 MHz for a 10 µA load current

Type: Conference Paper

Author : Haddad, P.-A.; Gosset, G.; Raskin, J.-P.; Flandre, D.

Publisher: IEEE

Year: 2014

Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors

Type: Conference Paper

Author : Assalti, R.; Pavanello, M.A.; de Souza, M.; Flandre, D.

Publisher: IEEE

Year: 2014

Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology

Type: Journal Paper

Author : Flandre, D.; Viviani, A.; Eggermont, J.-P.; Gentinne, B.; Jespers, P.G.A.

Year: 1997

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Carrier Mobility in Undoped Triple-Gate FinFET Structures and Limitations of Its Description in Terms of Top and Sidewall Channel Mobilities

Type: Journal Paper

Author : Rudenko, T.; Kilchytska, V.; Collaert, N.; Jurczak, M.; Nazarov, A.; Flandre, D.

Publisher: IEEE

Year: 2008

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On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part I—Effect of Gate-Voltage-Dependent Mobility

Type: Journal Paper

Author : Rudenko, T.; Kilchytska, V.; Arshad, M.K.M.; Raskin, J.-P.; Nazarov, A.; Flandre, D.

Publisher: IEEE

Year: 2011

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Quasi-double gate regime to boost UTBB SOI MOSFET performance in analog and sleep transistor applications

Type: Journal Paper

Author : Kilchytska, V.; Bol, D.; De Vos, J.; Andrieu, F.; Flandre, D.

Publisher: Elsevier Science

Year: 2013

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Temperature and back-gate bias influence on the operation of lateral SOI PIN photodiodes

Type: Conference Paper

Author : Novo, C.; Giacomini, R.; Doria, R.T.; Afzalian, A.; Flandre, D.

Publisher: IEEE

Year: 2014

Effect of the temperature on on Junctionless Nanowire Transistors electrical parameters down to 4K

Type: Conference Paper

Author : Trevisoli, R.; de Souza, M.; Doria, R.T.; Kilchtyska, V.; Flandre, D.; Pavanello, M.A.

Publisher: IEEE

Year: 2014

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A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

Dependence of the optimum length of light doped region of GC SOI nMOSFET with front gate bias

Efficient ultra low power rectification at 13.56 MHz for a 10 µA load current

Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors

Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology

Carrier Mobility in Undoped Triple-Gate FinFET Structures and Limitations of Its Description in Terms of Top and Sidewall Channel Mobilities

On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part I—Effect of Gate-Voltage-Dependent Mobility

Quasi-double gate regime to boost UTBB SOI MOSFET performance in analog and sleep transistor applications

Temperature and back-gate bias influence on the operation of lateral SOI PIN photodiodes

Effect of the temperature on on Junctionless Nanowire Transistors electrical parameters down to 4K

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A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA

Dependence of the optimum length of light doped region of GC SOI nMOSFET with front gate bias

Efficient ultra low power rectification at 13.56 MHz for a 10 &#x00B5;A load current

Technological parameters scaling influence on the analog performance of Graded-Channel SOI nMOSFET transistors

Improved synthesis of gain-boosted regulated-cascode CMOS stages using symbolic analysis and gm/ID methodology

Carrier Mobility in Undoped Triple-Gate FinFET Structures and Limitations of Its Description in Terms of Top and Sidewall Channel Mobilities

On the MOSFET Threshold Voltage Extraction by Transconductance and Transconductance-to-Current Ratio Change Methods: Part I—Effect of Gate-Voltage-Dependent Mobility

Quasi-double gate regime to boost UTBB SOI MOSFET performance in analog and sleep transistor applications

Temperature and back-gate bias influence on the operation of lateral SOI PIN photodiodes

Effect of the temperature on on Junctionless Nanowire Transistors electrical parameters down to 4K

Efficient ultra low power rectification at 13.56 MHz for a 10 µA load current