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Now showing items 1-7 of 7

Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias

Type: Journal Paper

Author : Yung-Fa Chou; Ding-Ming Kwai; Cheng-Wen Wu

Year: 2011

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Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults

Type: Journal Paper

Author : Yen-Lin Peng; Ding-Ming Kwai; Yung-Fa Chou; Cheng-Wen Wu

Publisher: IEEE

Year: 2014

Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization

Type: Journal Paper

Author : Chiao-Ling Lung; Yi-Lun Ho; Ding-Ming Kwai; Shih-Chieh Chang

Year: 2011

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A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

Type: Journal Paper

Author : Chih-Sheng Hou; Yong-Xiao Chen; Jin-Fu Li; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou

Year: 2016

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Hierarchical Test Integration Methodology for 3-D ICs

Type: Journal Paper

Author : Che-Wei Chou; Jin-Fu Li; Yun-Chao Yu; Chih-Yen Lo; Ding-Ming Kwai; Yung-Fa Chou

Year: 2015

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Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization

Type: Journal Paper

Author : Yu, Cody Hao; Chiao-Ling Lung; Yi-Lun Ho; Ruei-Siang Hsu; Ding-Ming Kwai; Shih-Chieh Chang

Publisher: IEEE

Year: 2014

DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool

Type: Journal Paper

Author : Hsiu-Chuan Shih; Pei-Wen Luo; Jen-Chieh Yeh; Shu-Yen Lin; Ding-Ming Kwai; Shih-Lien Lu; Schaefer, Anna; Cheng-Wen Wu

Publisher: IEEE

Year: 2014

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Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias

Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults

Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

Hierarchical Test Integration Methodology for 3-D ICs

Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization

DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool

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Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias

Application-Independent Testing of 3-D Field Programmable Gate Array Interconnect Faults

Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization

A built-in self-repair scheme for DRAMs with spare rows, columns, and bits

Hierarchical Test Integration Methodology for 3-D ICs

Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization

DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool