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Polarity-Controllable Silicon Nanowire Transistors With Dual Threshold Voltages

Type: Journal Paper

Author : Jian Zhang; De Marchi, Michele; Sacchetto, Davide; Gaillardon, Pierre-Emmanuel; Leblebici, Yusuf; De Micheli, G.

Publisher: IEEE

Year: 2014

Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity

Type: Journal Paper

Author : De Marchi, Michele; Sacchetto, Davide; Jian Zhang; Frache, Stefano; Gaillardon, Pierre-Emmanuel; Leblebici, Yusuf; De Micheli, G.

Publisher: IEEE

Year: 2014

Configurable Logic Gates Using Polarity-Controlled Silicon Nanowire Gate-All-Around FETs

Type: Journal Paper

Author : De Marchi, Michele; Jian Zhang; Frache, Stefano; Sacchetto, Davide; Gaillardon, Pierre-Emmanuel; Leblebici, Yusuf; De Micheli, G.

Publisher: IEEE

Year: 2014

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Polarity-Controllable Silicon Nanowire Transistors With Dual Threshold Voltages

Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity

Configurable Logic Gates Using Polarity-Controlled Silicon Nanowire Gate-All-Around FETs

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Polarity-Controllable Silicon Nanowire Transistors With Dual Threshold Voltages

Top&#x2013;Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity

Configurable Logic Gates Using Polarity-Controlled Silicon Nanowire Gate-All-Around FETs

Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity