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Author : Ingels, M.; Giannini, V.; Borremans, J.; Mandal, G.; Debaillie, B.; Van Wesemael, P.; Sano, T.; Yamamoto, T.; Hauspie, D.; Van Driessche, J.; Craninckx, J.

Year: 2010

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Low-noise voltage-controlled oscillators using enhanced LC-tanks

A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors

A 9.1–12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction

A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS

A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC

A Dual-Notch +27dBm Tx-Power Electrical-Balance Duplexer

A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and −58dBc C-IM3

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

A 5 mm 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform

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Low-noise voltage-controlled oscillators using enhanced LC-tanks

A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors

A 9.1&#x2013;12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction

A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS

A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC

A Dual-Notch +27dBm Tx-Power Electrical-Balance Duplexer

A linear 28nm CMOS digital transmitter with 2&#x00D7;12bit up to LO baseband sampling and &#x2212;58dBc C-IM3

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

A 5 mm 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform

A 9.1–12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction

A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and −58dBc C-IM3