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Now showing items 1-7 of 7

A novel architecture for dynamic integral image generation for Haar-based face detection on FPGA

Type: Conference Paper

Author : Kumar, Chanchal; Agarwal, Sankalp

Publisher: IEEE

Year: 2014

Band-Edge Steepness Obtained From Esaki/Backward Diode Current–Voltage Characteristics

Type: Journal Paper

Author : Agarwal, Sankalp; Yablonovitch, Eli

Publisher: IEEE

Year: 2014

Fundamental Conductance <inline-formula> <img src="/images/tex/21788.gif" alt="(\\div )"> </inline-formula> Voltage Limit in Low Voltage Tunnel Switches

Type: Journal Paper

Author : Agarwal, Sankalp; Yablonovitch, Eli

Publisher: IEEE

Year: 2014

Nitrogen-Terminated Semiconducting Zigzag GNR FET With Negative Differential Resistance

Type: Journal Paper

Author : Kumar, Ajit; Kumar, Vipin; Agarwal, Sankalp; Basak, Abhishek; Jain, Nikhil; Bulusu, Anand; Manhas, Sanjeev Kumar

Publisher: IEEE

Year: 2014

Engineering the Electron–Hole Bilayer Tunneling Field-Effect Transistor

Type: Journal Paper

Author : Agarwal, Sankalp; Teherani, James T.; Hoyt, Judy L.; Antoniadis, Dimitri /A/.; Yablonovitch, Eli

Publisher: IEEE

Year: 2014

Corrections to “Nitrogen Terminated Semiconducting Zigzag GNR FET with Negative Differential Resistance” [Jan 14 16-22]

Type: Journal Paper

Author : Kumar, Ajit; Kumar, Vipin; Agarwal, Sankalp; Basak, Abhishek; Jain, Nikhil; Bulusu, Anand; Manhas, Sanjeev Kumar

Publisher: IEEE

Year: 2014

Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs

Type: Journal Paper

Author : Nayak, Kaushik; Agarwal, Sankalp; Bajaj, Mohit; Oldiges, Philip J.; Murali, Kota V. R. M.; Rao, Valipe Ramgopal

Publisher: IEEE

Year: 2014

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A novel architecture for dynamic integral image generation for Haar-based face detection on FPGA

Band-Edge Steepness Obtained From Esaki/Backward Diode Current–Voltage Characteristics

Fundamental Conductance <inline-formula> <img src="/images/tex/21788.gif" alt="(\\div )"> </inline-formula> Voltage Limit in Low Voltage Tunnel Switches

Nitrogen-Terminated Semiconducting Zigzag GNR FET With Negative Differential Resistance

Engineering the Electron–Hole Bilayer Tunneling Field-Effect Transistor

Corrections to “Nitrogen Terminated Semiconducting Zigzag GNR FET with Negative Differential Resistance” [Jan 14 16-22]

Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs

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A novel architecture for dynamic integral image generation for Haar-based face detection on FPGA

Band-Edge Steepness Obtained From Esaki/Backward Diode Current&#x2013;Voltage Characteristics

Fundamental Conductance <inline-formula> <img src="/images/tex/21788.gif" alt="(\\div )"> </inline-formula> Voltage Limit in Low Voltage Tunnel Switches

Nitrogen-Terminated Semiconducting Zigzag GNR FET With Negative Differential Resistance

Engineering the Electron&#x2013;Hole Bilayer Tunneling Field-Effect Transistor

Corrections to &#x201C;Nitrogen Terminated Semiconducting Zigzag GNR FET with Negative Differential Resistance&#x201D; [Jan 14 16-22]

Metal-Gate Granularity-Induced Threshold Voltage Variability and Mismatch in Si Gate-All-Around Nanowire n-MOSFETs

Band-Edge Steepness Obtained From Esaki/Backward Diode Current–Voltage Characteristics

Engineering the Electron–Hole Bilayer Tunneling Field-Effect Transistor

Corrections to “Nitrogen Terminated Semiconducting Zigzag GNR FET with Negative Differential Resistance” [Jan 14 16-22]