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A Novel Vernier-based Time to Digital Converter for Low-power RFID Sensor Tags

Type: Conference Paper

Author : Shahrokhi, Seyed Hossein; Hosseinzadeh, Mehdi

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Improving DRAM performance by parallelizing refreshes with accesses

Type: Conference Paper

Publisher: IEEE

Year: 2014

FPGA implementation of an interior point method for high-speed model predictive control

Type: Conference Paper

Author : Junyi Liu; Peyrl, H.; Burg, A.; Constantinides, G.A.

Publisher: IEEE

Year: 2014

Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning

Type: Conference Paper

Author : Mingli Xie , Dong Tong , Kan Huang , Xu Cheng

Publisher: IEEE

Year: 2014

Modelling and analysis of wireless communication over Networks-on-Chip

Type: Conference Paper

Author : Kumar, A. , Kapoor, H.K.

Publisher: IEEE

Year: 2014

T-NOVA: A marketplace for virtualized network functions

Type: Conference Paper

Publisher: IEEE

Year: 2014

Loosely-Coupled Benchmark Framework Automates Performance Modeling on IaaS Clouds

Type: Conference Paper

Author : Ge, Xinni; Qi, Zhengwei; Chen, Ken; Duan, Jiangang; Dong, Zhenjiang

Publisher: IEEE

Year: 2014

A novel design of hollow microneedle for blood sample collection

Type: Conference Paper

Publisher: IEEE

Year: 2014

Towards WSN-aided navigation for vehicles in smart cities: An application case study

Type: Conference Paper

Author : Dagher, R. , Mitton, N. , Amadou, I.

Publisher: IEEE

Year: 2014

Time-to-Digital Converter Based on FPGA With Multiple Channel Capability

Type: Journal Paper

Author : Torres, Juana; Aguilar, Albert; Garcia-Olcina, R.; Martinez, Philip /A/.; Martos, J.; Soret, J.; Benlloch, J.M.; Conde, P.; Gonzalez, A.J.; Sanchez, F.

Publisher: IEEE

Year: 2014

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A Novel Vernier-based Time to Digital Converter for Low-power RFID Sensor Tags

Improving DRAM performance by parallelizing refreshes with accesses

FPGA implementation of an interior point method for high-speed model predictive control

Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning

Modelling and analysis of wireless communication over Networks-on-Chip

T-NOVA: A marketplace for virtualized network functions

Loosely-Coupled Benchmark Framework Automates Performance Modeling on IaaS Clouds

A novel design of hollow microneedle for blood sample collection

Towards WSN-aided navigation for vehicles in smart cities: An application case study

Time-to-Digital Converter Based on FPGA With Multiple Channel Capability

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A Novel Vernier-based Time to Digital Converter for Low-power RFID Sensor Tags

Improving DRAM performance by parallelizing refreshes with accesses

FPGA implementation of an interior point method for high-speed model predictive control

Improving system throughput and fairness simultaneously in shared memory CMP systems via Dynamic Bank Partitioning

Modelling and analysis of wireless communication over Networks-on-Chip

T-NOVA: A marketplace for virtualized network functions

Loosely-Coupled Benchmark Framework Automates Performance Modeling on IaaS Clouds

A novel design of hollow microneedle for blood sample collection

Towards WSN-aided navigation for vehicles in smart cities: An application case study

Time-to-Digital Converter Based on FPGA With Multiple Channel Capability