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Now showing items 1-7 of 7

Nano-scale CMOS SoC RF transceivers for 60 GHz wireless body area networks

Type: Conference Paper

Author : Zito, D. , Pepe, D.

Publisher: IEEE

Year: 2014

Design of a Temperature-Aware Low-Voltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 °C

Type: Journal Paper

Author : Kim, Tony Tae-Hyoung; Ngoc Le Ba

Publisher: IEEE

Year: 2014

Compiler-Assisted Leakage- and Temperature- Aware Instruction-Level VLIW Scheduling

Type: Journal Paper

Author : Shan Cao; Zhaolin Li; Fang Wang; Shaojun Wei

Publisher: IEEE

Year: 2014

Architectural Thermal Energy Harvesting Opportunities for Sustainable Computing

Type: Journal Paper

Author : Wu, Carole-Jean

Publisher: IEEE

Year: 2014

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

Type: Journal Paper

Author : Meng-Fan Chang; Chia-Chen Kuo; Shyh-Shyuan Sheu; Chorng-Jung Lin; Ya-Chin King; Chen, F.T.; Tzu-Kun Ku; Ming-Jinn Tsai; Jui-Jen Wu; Yue-Der Chih

Publisher: IEEE

Year: 2014

Supporting triple-play communications with TDuCSMA and first experiments

Type: Conference Paper

Author : Vesco, Andrea; Scopigno, Riccardo M.; Masala, Enrico

Publisher: IEEE

Year: 2014

An overview of speed control approaches to improve freeway traffic flow

Type: Conference Paper

Author : Hegyi, Andreas

Publisher: IEEE

Year: 2014

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Nano-scale CMOS SoC RF transceivers for 60 GHz wireless body area networks

Design of a Temperature-Aware Low-Voltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 °C

Compiler-Assisted Leakage- and Temperature- Aware Instruction-Level VLIW Scheduling

Architectural Thermal Energy Harvesting Opportunities for Sustainable Computing

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

Supporting triple-play communications with TDuCSMA and first experiments

An overview of speed control approaches to improve freeway traffic flow

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Nano-scale CMOS SoC RF transceivers for 60 GHz wireless body area networks

Design of a Temperature-Aware Low-Voltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 &#x00B0;C

Compiler-Assisted Leakage- and Temperature- Aware Instruction-Level VLIW Scheduling

Architectural Thermal Energy Harvesting Opportunities for Sustainable Computing

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme

Supporting triple-play communications with TDuCSMA and first experiments

An overview of speed control approaches to improve freeway traffic flow

Design of a Temperature-Aware Low-Voltage SRAM With Self-Adjustable Sensing Margin Enhancement for High-Temperature Applications up to 300 °C