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Stability analysis of broadband cascode amplifiers in the presence of inductive parasitic components

Type: Journal Paper

Author : Nikandish, Gholamreza; Yousefi, Alireza; Medi, Ali

Publisher: IET

Year: 2014

Low-voltage bulk-driven self-biased cascode current mirror with bandwidth enhancement

Type: Journal Paper

Author : Raj, Nistul; Singh, A.K.; Gupta, Amit Kumar

Publisher: IET

Year: 2014

Zero bit error rate id generation circuit using via formation probability in 0.18 μm CMOS process

Type: Journal Paper

Author : Kim, Tae Wook; Choi, B.D.; Kim, Duk Kyung

Publisher: IET

Year: 2014

Design and comparison of flipped active inductors with high quality factors

Type: Journal Paper

Author : Saberkari, Alireza; Ziabakhsh, S.; Martí nez, H.; Alarcó n, E.

Publisher: IET

Year: 2014

Design of ternary clock generator

Type: Journal Paper

Author : Yan-Feng Lang; Ji-Zhong Shen; Liang Geng; Mao-Qun Yao

Publisher: IET

Year: 2014

A Flexible, Self-Tuning, Fault-Tolerant Functional Unit Array Processor

Type: Journal Paper

Author : Jun Yao; Nakashima, Y.; Saito, M.; Hazama, Y.; Yamanaka, R.

Publisher: IEEE

Year: 2014

Parallel very large-scale integration chip implementation of optimal fractional motion estimation

Type: Journal Paper

Author : Shih-Chang Hsia; Lung-Sen Chen

Publisher: IET

Year: 2014

Area-efficient high-voltage switch using floating control circuit for 3D ultrasound imaging systems

Type: Journal Paper

Author : Sung-Jin Jung; Seong-Kwan Hong; Oh-Kyong Kwon

Publisher: IET

Year: 2014

Sub-harmonic upconversion mixer using 0.18 μm CMOS technology

Type: Journal Paper

Author : Jie Jin; Chunhua Wang; Zanming Xia; Huai Yang

Publisher: IET

Year: 2014

Author index

Type: Conference Paper

Publisher: IEEE

Year: 2014

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Stability analysis of broadband cascode amplifiers in the presence of inductive parasitic components

Low-voltage bulk-driven self-biased cascode current mirror with bandwidth enhancement

Zero bit error rate id generation circuit using via formation probability in 0.18 μm CMOS process

Design and comparison of flipped active inductors with high quality factors

Design of ternary clock generator

A Flexible, Self-Tuning, Fault-Tolerant Functional Unit Array Processor

Parallel very large-scale integration chip implementation of optimal fractional motion estimation

Area-efficient high-voltage switch using floating control circuit for 3D ultrasound imaging systems

Sub-harmonic upconversion mixer using 0.18 μm CMOS technology

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Stability analysis of broadband cascode amplifiers in the presence of inductive parasitic components

Low-voltage bulk-driven self-biased cascode current mirror with bandwidth enhancement

Zero bit error rate id generation circuit using via formation probability in 0.18 &#x003BC;m CMOS process

Design and comparison of flipped active inductors with high quality factors

Design of ternary clock generator

A Flexible, Self-Tuning, Fault-Tolerant Functional Unit Array Processor

Parallel very large-scale integration chip implementation of optimal fractional motion estimation

Area-efficient high-voltage switch using floating control circuit for 3D ultrasound imaging systems

Sub-harmonic upconversion mixer using 0.18 &#956;m CMOS technology

Author index

Zero bit error rate id generation circuit using via formation probability in 0.18 μm CMOS process

Sub-harmonic upconversion mixer using 0.18 μm CMOS technology