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    A 1-V Process-Insensitive Current-Scalable Two-Stage Opamp with Enhanced DC Gain and Settling Behavior in 65-nm Digital CMOS 

    Type: Journal Paper
    Author : محمد طاهرزاده ثانی; Anas A. Hamoui; Mohammad Taherzadeh-Sani
    Year: 2011
    Abstract:

    A pseudo-cascode compensation technique is proposed to enable a process-insensitive and current-scalable design of the classical two-stage opamp at low supply voltages, without requiring any additional power dissipation. Furthermore, a bulk...

    PLL-Assisted Timing Circuit for Accurate TSV Leakage Binning 

    Type: Journal Paper
    Author : Shi-Yu Huang; Li-Ren Huang
    Publisher: IEEE
    Year: 2014

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