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On-chip magnetic thin-film noise suppressor for IC chip level digital noise countermeasure

Type: Conference Paper

Author : Yamaguchi, Masahiro; Endo, Yasushi; Tanaka, Satoshi; Ito, Tetsuo; Muroga, Sho; Azuma, Naoya; Nagata, Makoto

Publisher: IEEE

Year: 2014

Advanced techniques for integration of energy storage and photovoltaic generator in renewable energy systems

Type: Conference Paper

Author : Dwari, Suman; Arnedo, Luis; Blasko, Vladimir

Publisher: IEEE

Year: 2014

Effects of graphitic nanomaterials on the dissociation pathway of amyloidogenic peptide dimer

Type: Conference Paper

Author : Makarucha, A.J.; Todorova, N.; Yarovsky, I.

Publisher: IEEE

Year: 2014

An analytical model for transfer characteristics and sub-threshold swings in double-gate tunnel FETs

Type: Conference Paper

Author : Gholizadeh, Mahdi; Hosseini, Seyed Ebrahim

Publisher: IEEE

Year: 2014

Low-latency last-level cache structure based on grouped cores in Chip Multi-Processor

Type: Conference Paper

Author : Jinbo Xu; Weixia Xu; Kefei Wang; Zhengbin Pang

Publisher: IEEE

Year: 2014

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Type: Conference Paper

Publisher: IEEE

Year: 2014

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On-chip magnetic thin-film noise suppressor for IC chip level digital noise countermeasure

Advanced techniques for integration of energy storage and photovoltaic generator in renewable energy systems

Effects of graphitic nanomaterials on the dissociation pathway of amyloidogenic peptide dimer

An analytical model for transfer characteristics and sub-threshold swings in double-gate tunnel FETs

Low-latency last-level cache structure based on grouped cores in Chip Multi-Processor

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On-chip magnetic thin-film noise suppressor for IC chip level digital noise countermeasure

Advanced techniques for integration of energy storage and photovoltaic generator in renewable energy systems

Effects of graphitic nanomaterials on the dissociation pathway of amyloidogenic peptide dimer

An analytical model for transfer characteristics and sub-threshold swings in double-gate tunnel FETs

Low-latency last-level cache structure based on grouped cores in Chip Multi-Processor

Committees