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A low-power architecture for integrating analog-to-digital converters
This paper reports on a modified architecture for
single-slope integrating analog-to-digital converter (ADC) for
use in image sensors and biomedical or any other applications
where the value of the ...
Detailed Study of the Time Estimation in Level-Crossing Analog-to-Digital Converters
Level-crossing analog-to-digital converters
(LC-ADCs) have shown to be power-efficient for a wide range of
applications where sparse signals are processed. In this paper,
after addressing different ...
Modified Structures for Power-Efficient Level Translators
Reducing the supply voltage of a digital integrated
circuit decreases the power consumption and also the circuit
speed. One effective way for low-power design of digital
integrated circuits is to employ two or multiple supply...
ON THE POWER EFFICIENCY OF CASCODE COMPENSATION OVER MILLER COMPENSATION IN TWO-STAGE OPERATIONAL AMPLIFIERS
Optimization of power consumption is one of the main design challenges in today’s lowpower
high-speed analog integrated circuits. In this paper, two popular techniques to
stabilize two-stage operational ...
A Novel Circuit Design Technique to Minimize Sleep Mode Power Consumption due to Leakage Power in the Sub-100nm Wide Gates in CMOS Technology
With the rapid scaling down of CMOS manufacturing technology, the reduction in leakage
power has become an important concern in low voltage, low power and high performance applications. In
this paper a novel ...
Power Reduction Techniques in a 6 bit 1 GSPS Flash ADC
Abstract-Flash Analog-to-Digital Converters (ADCs) are usually
used in high-speed yet low-resolution applications such as wideband
radio transceivers. Since the power consumption of such
ADCs exponentially ri
A 5.3-9.3 fJ/Conversion-Step 4-32 MS/s 10 bit Asynchronous SAR ADC with Optimized DAC Timing Strategy in 0.13 μm CMOS
In this paper, a low power SAR Analog to Digital
Converter (ADC) with a resolution of 10 bits and a sampling
rate of 4 to 32 MS/s is proposed. It utilizes an asynchronous
process with an optimized D/A ...