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PC-DUOS+: A TCAM Architecture for Packet Classifiers

Type: Journal Paper

Author : Banerjee, Taposh; Sahni, Shashank; Seetharaman, Guna

Publisher: IEEE

Year: 2014

Soft-error protection of TCAMs based on ECCs and asymmetric SRAM cells

Type: Journal Paper

Author : Gherman, V.; Cartron, M.

Publisher: IET

Year: 2014

Simultaneously Reducing Latency and Power Consumption in OpenFlow Switches

Type: Journal Paper

Author : Congdon, Paul T.; Mohapatra, Prasant; Farrens, Matthew; Akella, Venkatesh

Publisher: IEEE

Year: 2014

Efficient Register Renaming and Recovery for High-Performance Processors

Type: Journal Paper

Author : Petit, Stephane; Ubal, Rafael; Sahuquillo, Julio; Lopez, Pierre

Publisher: IEEE

Year: 2014

High-Throughput and Memory-Efficient Multimatch Packet Classification Based on Distributed and Pipelined Hash Tables

Type: Journal Paper

Author : Yang Xu; Zhaobo Liu; Zhuoyuan Zhang; Chao, H. Jonathan

Publisher: IEEE

Year: 2014

Efficient Cache Designs for Probabilistically Analysable Real-Time Systems

Type: Journal Paper

Author : Kosmidis, Leonidas; Abella, Jaume; Quinones, Eduardo; Cazorla, Francisco J.

Publisher: IEEE

Year: 2014

An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory

Type: Journal Paper

Author : Abbas, Saad Mutashar; Soonyoung Lee; Baeg, Sanghyeon; Sungju Park

Publisher: IEEE

Year: 2014

A Memory-Efficient TCAM Coprocessor for IPv4/IPv6 Routing Table Update

Type: Journal Paper

Author : Fang-Chen Kuo; Yeim-Kuan Chang; Cheng-Chien Su

Publisher: IEEE

Year: 2014

Large-Scale Memristive Associative Memories

Type: Journal Paper

Author : Lehtonen, Eero; Poikonen, Jussi H.; Laiho, Mika; Kanerva, Pentti

Publisher: IEEE

Year: 2014

1 Mb 0.41 µm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing

Type: Journal Paper

Author : Jing Li; Montoye, R.K.; Ishii, M.; Chang, Ly-Yu

Publisher: IEEE

Year: 2014

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PC-DUOS+: A TCAM Architecture for Packet Classifiers

Soft-error protection of TCAMs based on ECCs and asymmetric SRAM cells

Simultaneously Reducing Latency and Power Consumption in OpenFlow Switches

Efficient Register Renaming and Recovery for High-Performance Processors

High-Throughput and Memory-Efficient Multimatch Packet Classification Based on Distributed and Pipelined Hash Tables

Efficient Cache Designs for Probabilistically Analysable Real-Time Systems

An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory

A Memory-Efficient TCAM Coprocessor for IPv4/IPv6 Routing Table Update

Large-Scale Memristive Associative Memories

1 Mb 0.41 µm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing

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PC-DUOS+: A TCAM Architecture for Packet Classifiers

Soft-error protection of TCAMs based on ECCs and asymmetric SRAM cells

Simultaneously Reducing Latency and Power Consumption in OpenFlow Switches

Efficient Register Renaming and Recovery for High-Performance Processors

High-Throughput and Memory-Efficient Multimatch Packet Classification Based on Distributed and Pipelined Hash Tables

Efficient Cache Designs for Probabilistically Analysable Real-Time Systems

An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory

A Memory-Efficient TCAM Coprocessor for IPv4/IPv6 Routing Table Update

Large-Scale Memristive Associative Memories

1 Mb 0.41 &#x00B5;m&#x00B2; 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing

1 Mb 0.41 µm² 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing