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Instruction and Data Cache Peak Temperature Reduction Using Cache Access Balancing in Embedded Processors
Year: 2011
Abstract:
In this work we study cache peak temperature
variation under different cache access patterns. In particular we
show that unbalanced cache access results in higher cache peak
temperature. This is the ...
Measurement of the latency parameters of the Multi-BSP model: a multicore benchmarking approach
Year: 2013
Abstract:
Multi-Bulk Synchronous
Parallel (Multi-BSP). This method measures the hardware latency parameters of multicore
computers, namely communication latency (gi ) and synchronization latency
(Li ) for all levels of the cache memory...
PAPR reduction of OFDM system using PTS method with different modulation techniques
Publisher: IEEE
Year: 2014
A surface plasmon polariton analogue of a Wannier-Stark ladder
Publisher: IEEE
Year: 2014
A bridging model for branch-and-bound algorithmson multi-core architectures
Year: 2012
Abstract:
By emerging the multi-core architectures, the efficient exploitation of these architectures becomes a very serious issue. The evolution of these architectures goes towards increasing the number of cores and levels of cache. ...
Digital modulation recognition using circular harmonic approximation of likelihood function
Publisher: IEEE
Year: 2014
Application of ADRC in hydraulic AGC system
Publisher: IEEE
Year: 2014