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Parasitic Back-Gate Effect in 3-D Fully Depleted Silicon on Insulator Integrated Circuits

Type: Journal Paper

Author : Gaynor, Brad D.; Hassoun, Soha

Publisher: IEEE

Year: 2014

Fabrication and Testing of a TSV-Enabled Si Interposer With Cu- and Polymer-Based Multilevel Metallization

Type: Journal Paper

Author : Lannon, J.; Hilton, Adrian; Huffman, Alan; Butler, Mairead; Malta, D.; Gregory, Chris; Temple, D.

Publisher: IEEE

Year: 2014

Author

Butler, Mairead (1)

Gaynor, Brad D. (1)

Gregory, Chris (1)

Hassoun, Soha (1)

Hilton, Adrian (1)

Huffman, Alan (1)

Lannon, J. (1)

Malta, D. (1)

Temple, D. (1)

Publisher

IEEE (2)

Year

2014 (2)

Keywords

backside metal layer (2)

integrated circuit testing (2)

Si (2)

silicon (2)

three-dimensional integrated circuits (2)

3D fully depleted silicon (1)

3D heterogeneous integration applications (1)

3D integrated circuits (1)

3D integration (1)

3D interposer test vehicle (1)

Type

Journal Paper (2)

Language (ISO)

English (2)

Content Type

Metadata Only (2)

Publication Title

Components, Packaging and Manufacturing Technology, IEEE Transactions on (2)

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