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A New Design Technique for Low Power Subthreshold Logic Circuits with Enhanced Robustness Against Process Variations
Abstract— Designing logic circuits in the subthreshold regime is
one of the most effective ways to reduce the power consumption
of digital circuits. In the subthreshold region, the current is an
exponential ...
A low-power wide-range voltage level shifter using a modified Wilson current mirror
In this paper, a low-power voltage level shifter is proposed which is able to convert sub-threshold voltage levels of input signal to above-threshold voltage levels. The proposed circuit is based on a modified Wilson current mirror structure which...
A Low-Power Level-Shifting Architecture for Sub-threshold Logic Circuits
This paper presents a power-efficient voltage level shifter converting low levels of input voltages (sub-threshold) to high levels of the output voltages (above threshold). In order to reduce the existing contention in the output nodes between pull...
An Energy-Efficient Level Shifter for Low-Power Applications
One effective way to reduce the power consumption of biomedical implantable devices is to employ different supply voltages for different parts of the system depending on the processing speed of each part. This, however, ...
Design and Optimization of a P+N+IN+ Tunnel FET with Si Channel and SiGe Source
are obtained. Moreover, the ource/channel hetero-junction is assumed graded. The grading distance is varied from zero (abrupt hetero-junction) to total channel length to achieve the best performance, i.e. low off state current, high Ion/Ioff and low sub-threshold...