Show simple item record

Modeling cache coherence misses on multicores

contributor authorXiaoyue Pan , Jonsson, B.
date accessioned2020-03-12T19:59:05Z
date available2020-03-12T19:59:05Z
date issued2014
identifier other6844465.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/997552?show=full
formatgeneral
languageEnglish
publisherIEEE
titleModeling cache coherence misses on multicores
typeConference Paper
contenttypeMetadata Only
identifier padid8117526
subject keywordsMOSFET
subject keywordsrandom-access storage
subject keywords1 transistor floating body dynamic random access memory application
subject keywords1T-FBRAM application
subject keywordsAC measurements
subject keywordsDC measurements
subject keywordsFBE
subject keywordsalternating current measurements
subject keywordsbiristor
subject keywordsbulk contact
subject keywordscharge storage
subject keywordsdirect current measurements
subject keywordsfloating body effect
subject keywordsjunction capacitor
subject keywordsreal memory operation
subject keywordstriple gate n-channel bulk FinFET
subject keywordsCurrent measurement
subject keywordsFinFETs
subject keywordsHysteresis
subject keywordsJunctions
subject keywordsLogic gates
subject keywordsRandom access memory
subject keywordsBulk
subject keywordsFinFET
subject keywordsback bias
subject keywordsfloating body effect
subject keywordsm
identifier doi10.1109/ICCDCS.2014.7016147
journal titleerformance Analysis of Systems and Software (ISPASS), 2014 IEEE International Symposium on
filesize373829
citations2


Files in this item

FilesSizeFormatView

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record