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An adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems

contributor authorCastellana, V.G. , Tumeo, A. , Ferrandi, F.
date accessioned2020-03-12T19:40:33Z
date available2020-03-12T19:40:33Z
date issued2014
identifier other6800393.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/985792?show=full
formatgeneral
languageEnglish
publisherIEEE
titleAn adaptive Memory Interface Controller for improving bandwidth utilization of hybrid and reconfigurable systems
typeConference Paper
contenttypeMetadata Only
identifier padid8101490
subject keywordsMOSFET
subject keywordsSRAM chips
subject keywordslogic circuits
subject keywordsoscillators
subject keywordsprocess monitoring
subject keywordssemiconductor device testing
subject keywordsNMOS
subject keywordsSOC designs
subject keywordsSRAM read current variability
subject keywordsbody bias based process corner correction
subject keywordscorner skew lots
subject keywordsdie as-fabricated process corners
subject keywordsdigital circuits
subject keywordsdigital outputs
subject keywordsembedded microprocessors
subject keywordsintegrated blocks
subject keywordslogic circuits
subject keywordslogic ring oscillators
subject keywordson-die PMOS
subject keywordsparametric yield correction
subject keywordspower correction
subject keywordsprocess monitors
subject keywordssize 55 nm
subject keywordsCurrent measurement
subject keywordsDelays
subject keywordsMOS devices
subject keywordsMir
identifier doi10.1109/CICC.2014.6946092
journal titleesign, Automation and Test in Europe Conference and Exhibition (DATE), 2014
filesize227751
citations0


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