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The Well-Connected Processor Array

contributor authorGordon, D.
date accessioned2020-03-12T18:20:55Z
date available2020-03-12T18:20:55Z
date issued2014
identifier issn0018-9340
identifier other6361379.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/955525?show=full
formatgeneral
languageEnglish
publisherIEEE
titleThe Well-Connected Processor Array
typeJournal Paper
contenttypeMetadata Only
identifier padid7987194
subject keywordsfast Fourier transforms
subject keywordsgraph theory
subject keywordsmultiprocessor interconnection networks
subject keywordsnetwork routing
subject keywordsreconfigurable architectures
subject keywordsPE
subject keywordsRMESH
subject keywordsWECPAR connectivity
subject keywordsbroadcasting
subject keywordscomplex switching configurations
subject keywordsgraph embeddings
subject keywordslogarithmic time
subject keywordsn-point FFT
subject keywordspoint-to-point lines
subject keywordsprocessing element
subject keywordsreconfigurable buses
subject keywordsreconfigurable mesh
subject keywordsreconfigurable processor arrays
subject keywordsself-simulation
subject keywordsswitch area
subject keywordstransportation-type routing method
subject keywordswell-connected processor array
subject keywordsBinary trees
subject keywordsComputer graph
identifier doi10.1109/TC.2012.280
journal titleComputers, IEEE Transactions on
journal volume63
journal issue5
filesize1613873
citations0


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