A New Design Technique for Low Power Subthreshold Logic Circuits with Enhanced Robustness Against Process Variations
Author:
, , ,Year
: 2013
Abstract: Abstract— Designing logic circuits in the subthreshold regime is
one of the most effective ways to reduce the power consumption
of digital circuits. In the subthreshold region, the current is an
exponential function of the threshold voltage and the behavior of
transistors is more susceptible to process variations. In this
paper, we present a new design technique that helps reduce the
impact of process variations on the circuit. The proposed
technique is implemented on the staticC2MOS flip-flop and the
flip flop is used in a shift register. The circuit is simulated in the
90nm CMOS technology using a 0.2V supply voltage. Simulation
results show that the robustness of the circuit is improved while
the power consumption and the area are kept at minimum.
one of the most effective ways to reduce the power consumption
of digital circuits. In the subthreshold region, the current is an
exponential function of the threshold voltage and the behavior of
transistors is more susceptible to process variations. In this
paper, we present a new design technique that helps reduce the
impact of process variations on the circuit. The proposed
technique is implemented on the staticC2MOS flip-flop and the
flip flop is used in a shift register. The circuit is simulated in the
90nm CMOS technology using a 0.2V supply voltage. Simulation
results show that the robustness of the circuit is improved while
the power consumption and the area are kept at minimum.
Keyword(s): Digital circuit,CMOS,Sub-threshold,robustness,low power
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A New Design Technique for Low Power Subthreshold Logic Circuits with Enhanced Robustness Against Process Variations
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| contributor author | سیده ساره مجیدی ایوری | en |
| contributor author | محمد میمندی نژاد | en |
| contributor author | Seyedeh Sareh Majidi Ivari | fa |
| contributor author | Mohammad Maymandi Nejad | fa |
| date accessioned | 2020-06-06T14:10:37Z | |
| date available | 2020-06-06T14:10:37Z | |
| date copyright | 5/14/2013 | |
| date issued | 2013 | |
| identifier uri | http://libsearch.um.ac.ir:80/fum/handle/fum/3385641 | |
| description abstract | Abstract— Designing logic circuits in the subthreshold regime is one of the most effective ways to reduce the power consumption of digital circuits. In the subthreshold region, the current is an exponential function of the threshold voltage and the behavior of transistors is more susceptible to process variations. In this paper, we present a new design technique that helps reduce the impact of process variations on the circuit. The proposed technique is implemented on the staticC2MOS flip-flop and the flip flop is used in a shift register. The circuit is simulated in the 90nm CMOS technology using a 0.2V supply voltage. Simulation results show that the robustness of the circuit is improved while the power consumption and the area are kept at minimum. | en |
| language | English | |
| title | A New Design Technique for Low Power Subthreshold Logic Circuits with Enhanced Robustness Against Process Variations | en |
| type | Conference Paper | |
| contenttype | External Fulltext | |
| subject keywords | Digital circuit | en |
| subject keywords | CMOS | en |
| subject keywords | Sub-threshold | en |
| subject keywords | robustness | en |
| subject keywords | low power | en |
| identifier link | https://profdoc.um.ac.ir/paper-abstract-1035639.html | |
| conference title | بیست و یکمین کنفرانس مهندسی برق ایران | fa |
| conference location | مشهد | fa |
| identifier articleid | 1035639 |