A Novel Congestion Control Scheme in Network-on-Chip Based on Best Effort Delay-Sum Optimization

Abstract

With the advances of the semiconductor technology,<br><br>the enormous number of transistors available on a<br><br>single chip allows designers to integrate dozens of IP<br><br>blocks together with large amounts of embedded<br><br>memory. This has been led to the concept of Network<br><br>on a Chip (NoC), in which different modules would be<br><br>connected by a simple network of shared links and<br><br>routers and is considered as a solution to replace<br><br>traditional bus-based architectures to address the<br><br>global communication challenges in nanoscale<br><br>technologies. In NoC architectures, controlling<br><br>congestion of the best effort traffic will continue to be<br><br>an important design goal. Towards this, employing<br><br>end-to-end congestion control is becoming more<br><br>imminent in the design process of NoCs. In this paper,<br><br>we introduce a centralized algorithm based on the<br><br>delay minimization of Best Effort sources. The<br><br>proposed algorithm can be used as a mechanism to<br><br>control the flow of Best Effort source rates by which<br><br>the sum of propagation delays of network is to be<br><br>minimized.