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A Parallel Radix-Sort-Based VLSI Architecture for Finding the First <inline-formula> <img src="/images/tex/473.gif" alt="W"> </inline-formula> Maximum/Minimum Values

contributor authorGuoping Xiao
contributor authorMartina, Maurizio
contributor authorMasera, Guido
contributor authorPiccinini, G.
date accessioned2020-03-13T00:19:32Z
date available2020-03-13T00:19:32Z
date issued2014
identifier issn1549-7747
identifier other6881635.pdf
identifier urihttp://libsearch.um.ac.ir:80/fum/handle/fum/1142558?show=full
formatgeneral
languageEnglish
publisherIEEE
titleA Parallel Radix-Sort-Based VLSI Architecture for Finding the First <inline-formula> <img src="/images/tex/473.gif" alt="W"> </inline-formula> Maximum/Minimum Values
typeJournal Paper
contenttypeMetadata Only
identifier padid8325101
subject keywordsVLSI
subject keywordscodecs
subject keywordslogic circuits
subject keywordslogic design
subject keywordsparallel architectures
subject keywordsparity check codes
subject keywordsturbo codes
subject keywordsBWA architecture
subject keywordsK-best multiple-input-multiple-output detectors
subject keywordsMIMO detectors
subject keywordsarea-delay product
subject keywordsbit-wise-and architecture
subject keywordshigh-speed CMOS standard-cell technology
subject keywordsmaximum/minimum values
subject keywordsnonbinary low-density-parity-check decoders
subject keywordsparallel radix-sort-based VLSI architecture
subject keywordssize 90 nm
subject keywordsturbo product codes
subject keywordsvery simple logic circuits
subject keywordsvery-large-scale integration architectures
subject keywordsComputer
identifier doi10.1109/TCSII.2014.2350333
journal titleCircuits and Systems II: Express Briefs, IEEE Transactions on
journal volume61
journal issue11
filesize543599
citations0


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